The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2013

Filed:

Aug. 06, 2007
Applicants:

Steven T. Mayer, Lake Oswego, OR (US);

Mark L. Rea, Tigard, OR (US);

Richard S. Hill, Atherton, CA (US);

Avishai Kepten, Lake Oswego, OR (US);

R. Marshall Stowell, Wilsonville, OR (US);

Eric G. Webb, Tigard, OR (US);

Inventors:

Steven T. Mayer, Lake Oswego, OR (US);

Mark L. Rea, Tigard, OR (US);

Richard S. Hill, Atherton, CA (US);

Avishai Kepten, Lake Oswego, OR (US);

R. Marshall Stowell, Wilsonville, OR (US);

Eric G. Webb, Tigard, OR (US);

Assignee:

Novellus Systems, Inc., Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C23F 1/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.


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