Chandler, AZ, United States of America

Digvijay Ashokkumar Raorane

This inventor holds 45 USPTO granted patents and 18 published patent applications and 2 EPO patents, primarily in Semiconductor Packaging. Top assignees: Intel Corporation, Applied Materials, Inc.. Active years: 2012-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Digvijay Ashokkumar Raorane. Retrieved from https://idiyas.com/inventor/digvijay-ashokkumar-raorane

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 45 

% Patents Active = 93.3

 

Average Co-Inventor Count = 2.7

ph-index = 5

Forward Citations = 221(Granted Patents)


Company Filing History:


Years Active: 2012-2026

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Areas of Expertise:
Electronic Package Assembly
Heterogeneous Integration
Through-Silicon Vias
Multi-Chip Unit
Embedded Communication Cavity
Ceramic Interposers
Warpage Control
Electromagnetic Interference Shielding
High Frequency Waveguide
Die Sidewall Interconnects
Bumpless Build-Up Layer
Tamper Resistant Lock Assembly
45 patents (USPTO):Explore Patents

Title: Exploring the Innovations of Digvijay Ashokkumar Raorane

Introduction: Digvijay Ashokkumar Raorane is a notable inventor based in Chandler, AZ, USA, known for his substantial contributions to the field of electronic packaging. With an impressive portfolio of 44 patents, Raorane has been at the forefront of developing technologies that enhance the efficiency and performance of integrated circuits (ICs).

Latest Patents: Among Raorane's latest patents are two groundbreaking innovations. The first is related to "Nested architectures for enhanced heterogeneous integration," which includes electronic packages and methods for forming such packages. This patent describes an electronic package with a base substrate that has multiple through substrate vias, accommodating designs with specialized cavities and components for improved integration.

The second innovation is the "IC package including multi-chip unit with bonded integrated heat spreader." This patent outlines a multi-chip unit designed for chip-level packaging, where multiple IC chips are interconnected through a metal redistribution structure and directly bonded to an integrated heat spreader. This direct bonding eliminates the need for thermal interface material, thereby reducing bond line thickness and enhancing thermal efficiency.

Career Highlights: Digvijay has contributed significantly to the tech industry through his work with leading companies such as Intel Corporation and Applied Materials, Inc. His experience at these organizations underscores his expertise in electronic packaging and semiconductor technologies.

Collaborations: Throughout his career, Raorane has collaborated with esteemed colleagues, including Ravindranath Vithal Mahajan and Debendra Mallik. These partnerships have fostered a rich environment of innovation and shared expertise, further propelling advancements in their respective fields.

Conclusion: Digvijay Ashokkumar Raorane exemplifies the spirit of innovation in electronic packaging. His numerous patents and collaborative efforts highlight his commitment to advancing technology and establishing new standards in the industry. As he continues to push the boundaries of what is possible, his contributions will undoubtedly have a lasting impact on the future of integrated circuits.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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