The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2023

Filed:

Dec. 27, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Debendra Mallik, Chandler, AZ (US);

Ravindranath Mahajan, Chandler, AZ (US);

Digvijay Raorane, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/495 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/367 (2013.01); H01L 21/4853 (2013.01); H01L 21/56 (2013.01); H01L 21/565 (2013.01); H01L 23/3107 (2013.01); H01L 23/3128 (2013.01); H01L 23/49568 (2013.01); H01L 23/5386 (2013.01); H01L 24/08 (2013.01); H01L 24/16 (2013.01); H01L 24/20 (2013.01); H01L 24/24 (2013.01); H01L 24/29 (2013.01); H01L 24/83 (2013.01); H01L 2224/02371 (2013.01);
Abstract

A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.


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