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For the Inventor, By the Inventor

Wielkopolski, Poland

Dariusz Czysz

USPTO Granted Patents = 13 


Average Co-Inventor Count = 4.6

ph-index = 6

Forward Citations = 156(Granted Patents)


Location History:

  • 60-965 Poznan, PL (2010)
  • Ostrow Wielkopolski, PL (2011 - 2012)
  • Poznan, PL (2011 - 2014)
  • Wielkopolski, PL (2012 - 2018)

Company Filing History:

goldMedal11 out of 672 
 
Mentor Graphics Corporation
 patents
silverMedal2 out of 832,812 
Other
 patents

Years Active: 2010-2018

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13 patents (USPTO):Explore Patents
1. 9874606 - Selective per-cycle masking of scan chains for system level test (2018-01-23),
2. 9377508 - Selective per-cycle masking of scan chains for system level test (2016-06-28),
3. 8832512 - Low power compression of incompatible test cubes (2014-09-09),
4. 8726113 - Selective per-cycle masking of scan chains for system level test (2014-05-13),
5. 8347159 - Compression based on deterministic vector clustering of incompatible test cubes (2013-01-01),
6. 8301945 - Decompressors for low power decompression of test patterns (2012-10-30),
7. 8290738 - Low power scan testing techniques and apparatus (2012-10-16),
8. 8166359 - Selective per-cycle masking of scan chains for system level test (2012-04-24),
9. 8046653 - Low power decompression of test cubes (2011-10-25),
10. 8015461 - Decompressors for low power decompression of test patterns (2011-09-06),
11. 7925465 - Low power scan testing techniques and apparatus (2011-04-12),
12. 7797603 - Low power decompression of test cubes (2010-09-14),
13. 7647540 - Decompressors for low power decompression of test patterns (2010-01-12),

Title: Dariusz Czysz: Innovator in Integrated Circuit Testing

Introduction

Dariusz Czysz is a notable inventor based in Wielkopolski, Poland, with a remarkable portfolio of 13 patents. His work primarily focuses on advanced methodologies for integrated circuit testing, contributing significantly to the field of electronic engineering.

Latest Patents

Among his latest innovations is the patent titled "Selective per-cycle masking of scan chains for system level test." This invention introduces built-in self-test techniques designed to address the challenges posed by unknown states in integrated circuits. Key features of this patent include a specialized scan chain selector integrated with a time compactor, which enhances the efficiency of masking unknown "X" states. It also outlines several important methods, including:

1. An architecture of a selector capable of operating with multiple scan chains and time compactors.

2. A method for determining and encoding per-cycle scan chain selection masks, which are crucial for suppressing unknown states.

3. A strategy to manage the phenomenon of over-masking.

Career Highlights

Throughout his career, Dariusz Czysz has garnered expertise and experience through his work with Mentor Graphics Corporation, among other companies. His innovations have played a significant role in transforming testing methodologies for integrated circuits, pushing the boundaries of what is possible in electronic design automation.

Collaborations

Dariusz has collaborated with several esteemed colleagues, including Janusz Rajski and Grzegorz Mrugalski. These partnerships have fostered an environment of creativity and innovation, further enhancing the impact of their collective work in the realm of integrated circuit testing.

Conclusion

Dariusz Czysz stands out as a prominent inventor whose contributions to integrated circuit technologies continue to influence industry standards and practices. His inventions, particularly in the area of selective masking techniques, are a testament to his commitment to innovation and excellence in engineering. As he continues to develop groundbreaking solutions, the field of electronic testing is sure to benefit from his expertise and visionary approach.

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