The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2014

Filed:

Mar. 16, 2011
Applicants:

Dariusz Czysz, Poznan, PL;

Grzegorz Mrugalski, Swarzedz, PL;

Nilanjan Mukherjee, Wilsonville, OR (US);

Janusz Rajski, West Linn, OR (US);

Przemyslaw Szczerbicki, Wielkopolski, PL;

Jerzy Tyszer, Poznan, PL;

Inventors:

Dariusz Czysz, Poznan, PL;

Grzegorz Mrugalski, Swarzedz, PL;

Nilanjan Mukherjee, Wilsonville, OR (US);

Janusz Rajski, West Linn, OR (US);

Przemyslaw Szczerbicki, Wielkopolski, PL;

Jerzy Tyszer, Poznan, PL;

Assignee:

Mentor Graphics Corporation, Wilsonville, OR (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed are representative embodiments of methods, apparatus, and systems for power aware test applications involving deterministic clustering of test cubes with conflicts. Embodiments of the disclosed technology can be used to generate low toggling parent patterns to reduce power consumption during testing an integrated circuit. The power consumption may be further reduced by generating low toggling control patterns.


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