The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 16, 2012
Filed:
Mar. 16, 2011
Xijiang Lin, West Linn, OR (US);
Dariusz Czysz, Ostrow Wielkopolski, PL;
Mark Kassab, Wilsonville, OR (US);
Grzegorz Mrugalski, Wilsonville, OR (US);
Janusz Rajski, West Linn, OR (US);
Jerzy Tyszer, Poznan, PL;
Xijiang Lin, West Linn, OR (US);
Dariusz Czysz, Ostrow Wielkopolski, PL;
Mark Kassab, Wilsonville, OR (US);
Grzegorz Mrugalski, Wilsonville, OR (US);
Janusz Rajski, West Linn, OR (US);
Jerzy Tyszer, Poznan, PL;
Mentor Graphics Corporation, Wilsonville, OR (US);
Abstract
Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test ('EDT') architecture). Among the disclosed embodiments are integrated circuits having programmable test stimuli selectors, programmable scan enable circuits, programmable clock enable circuits, programmable shift enable circuits, and/or programmable reset enable circuits. Exemplary test pattern generation methods that can be used to generate test patterns for use with any of the disclosed embodiments are also disclosed.