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For the Inventor, By the Inventor

Beaverton, OR, United States of America

Curtis Tsai

This inventor holds 30 USPTO granted patents and 6 published patent applications and 4 EPO patents, primarily in High Voltage Transistors. Top assignees: Intel Corporation, Analog Devices,inc.. Active years: 1999-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Curtis Tsai. Retrieved from https://idiyas.com/inventor/curtis-tsai

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 30 

% Patents Active = 90.0

 

Average Co-Inventor Count = 5.7

ph-index = 6

Forward Citations = 88(Granted Patents)


Location History:

  • Portland, OR (US) (2014)
  • Beaveton, OR (US) (2023)
  • Beaverton, OR (US) (1999 - 2024)

Company Filing History:

goldMedal29 out of 56,290 
 
Intel Corporation
 patents
silverMedal1 out of 3,699 
 
Analog Devices,inc.
 patents

Years Active: 1999-2026

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Areas of Expertise:
Nanowire Transistors
Gate Dielectric Transistors
Tri-Gate Process
High Voltage Devices
Integrated Circuit Structures
Vertical Transistors
Electrostatic Discharge
System-On-Chip
Precision Resistor
Non-Planar Devices
Bipolar Transistor
Antifuse Element
30 patents (USPTO):Explore Patents
1. 12568643 - Nanowire transistors and methods of fabrication (2026-03-03),
2. 12520578 - Methods of integrating multiple gate dielectric transistors on a tri-gate (finfet) process (2026-01-06),
3. 12471354 - Dipole threshold voltage tuning for high voltage transistor stacks (2025-11-11),
4. 12317590 - Substrate-free integrated circuit structures (2025-05-27),
5. 12166031 - Substrate-less electrostatic discharge (ESD) integrated circuit structures (2024-12-10),
6. 12136628 - High voltage three-dimensional devices having dielectric liners (2024-11-05),
7. 11881486 - High voltage three-dimensional devices having dielectric liners (2024-01-23),
8. 11695008 - Methods of integrating multiple gate dielectric transistors on a tri-gate (FINFET) process (2023-07-04),
9. 11610917 - High voltage three-dimensional devices having dielectric liners (2023-03-21),
10. 11251201 - High voltage three-dimensional devices having dielectric liners (2022-02-15),
11. 10847544 - High voltage three-dimensional devices having dielectric liners (2020-11-24),
12. 10692888 - High voltage three-dimensional devices having dielectric liners (2020-06-23),
13. 10658361 - Methods of integrating multiple gate dielectric transistors on a tri-gate (FINFET) process (2020-05-19),
14. 10505034 - Vertical transistor using a through silicon via gate (2019-12-10),
15. 10263112 - Vertical non-planar semiconductor device for system-on-chip (SoC) applications (2019-04-16),

Title: The Innovative Contributions of Curtis Tsai

Introduction

Curtis Tsai, based in Beaverton, Oregon, has made significant strides in the field of semiconductor technology. With a portfolio of 26 patents, he has consistently contributed to innovations that enhance the performance and reliability of electronic devices. His work showcases a blend of creativity and technical expertise.

Latest Patents

Among his latest innovations, Curtis has developed groundbreaking patents related to substrate-less electrostatic discharge (ESD) integrated circuit structures. These patents describe methods for fabricating integrated circuits that eliminate the need for substrates, featuring unique designs like fins protruding from semiconductor pedestals. The integration of N-type and P-type regions creates a P/N junction, contributing to enhanced device performance.

Another notable patent involves high voltage three-dimensional devices utilizing dielectric liners, which facilitate improved device architecture and efficiency. This semiconductor structure comprises multiple fin active regions, each equipped with complex gate structures made from layered dielectrics, optimizing the functioning of high voltage electronics.

Career Highlights

Curtis has held influential roles at prestigious companies, including Intel Corporation and Analog Devices, Inc. His work at these organizations underscored his capability to push the boundaries of semiconductor innovation. With a keen focus on research and development, he has fostered advancements that have far-reaching implications in technology.

Collaborations

Throughout his career, Curtis has collaborated with esteemed colleagues, including Walid M. Hafez and Chia-Hong Jan. These collaborations have played a crucial role in his patent developments and have allowed for the exchange of diverse ideas, enhancing the overall quality of the inventions produced.

Conclusion

Curtis Tsai stands out as a vital figure in semiconductor innovation. His extensive patent portfolio not only signifies his contributions but also highlights his commitment to enhancing electronic devices' performance. Through his work and collaborations, he continues to influence the landscape of technology, demonstrating the power of ingenuity and perseverance in the field of electronics.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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