The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2019

Filed:

Jun. 19, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Xiaodong Yang, Portland, OR (US);

Jui-Yen Lin, Hillsboro, OR (US);

Kinyip Phoa, Beaverton, OR (US);

Nidhi Nidhi, Hillsboro, OR (US);

Yi Wei Chen, Hillsboro, OR (US);

Kun-Huan Shih, Portland, OR (US);

Walid M. Hafez, Portland, OR (US);

Curtis Tsai, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 23/48 (2006.01); H01L 29/94 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7813 (2013.01); H01L 23/481 (2013.01); H01L 29/0653 (2013.01); H01L 29/66734 (2013.01); H01L 29/7809 (2013.01); H01L 29/945 (2013.01);
Abstract

A vertical transistor is described that uses a through silicon via as a gate. In one example, the structure includes a substrate, a via in the substrate, the via being filled with a conductive material and having a dielectric liner, a deep well coupled to the via, a drain area coupled to the deep well having a drain contact, a source area between the drain area and the via having a source contact, and a gate contact over the via.


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