The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 11, 2025
Filed:
Dec. 23, 2020
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Robin Chao, Portland, OR (US);
Bishwajeet Guha, Hillsboro, OR (US);
Brian Greene, Portland, OR (US);
Chung-Hsun Lin, Portland, OR (US);
Curtis Tsai, Beaverton, OR (US);
Orb Acton, Portland, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 84/03 (2025.01); H10D 84/01 (2025.01); H10D 84/83 (2025.01); H10D 86/00 (2025.01); H10D 86/01 (2025.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H10D 84/0142 (2025.01); H10D 84/0144 (2025.01); H10D 84/83 (2025.01); H10D 86/01 (2025.01); H10D 86/201 (2025.01);
Abstract
Integrated circuitry comprising high voltage (HV) and low voltage (LV) ribbon or wire (RoW) transistor stack structures. In some examples, a gate electrode of the HV and LV transistor stack structures may include the same work function metal. A metal oxide may be deposited around one or more channels of the HV transistor stack, thereby altering the dipole properties of the gate insulator stack from those of the LV transistor stack structure.