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For the Inventor, By the Inventor

Westminster, CA, United States of America

Clarence W Padgett

This inventor holds 25 USPTO granted patents, primarily in VLSI Memory Circuits. Top assignees: Creative Integrated Systems, Inc., Rockwell International Corporation, Rocoh Company, Ltd.. Active years: 1976-1999.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Clarence W Padgett. Retrieved from https://idiyas.com/inventor/clarence-w-padgett

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 25

% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 12

Forward Citations = 291(Granted Patents)


Location History:

  • Fountain Valley, CA (US) (1976)
  • Costa Mesa, CA (US) (1976)
  • Westminster, CA (US) (1976 - 1999)

Company Filing History:

goldMedal14 out of 20 
 
Creative Integrated Systems, Inc.
 patents
silverMedal10 out of 3,430 
 
Rockwell International Corporation
 patents
bronzeMedal3 out of 6 
 
Rocoh Company, Ltd.
 patents
4. 1 out of 1 
 
Creative Integrated Ststems, Inc.
 patent
where one patent can have more than one assignee

Years Active: 1976-1999

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Areas of Expertise:
VLSI Memory
Semiconductor ROM
Driver Circuit
High-Speed Memory
Memory Circuit
Timing Adjustor
Static Read Only Memory
CMOS Logic
Differential Amplifier
Level Shifting Circuit
Memory Clocking
Core Memory
25 patents (USPTO):Explore Patents
1. 6002618 - NMOS input receiver circuit (1999-12-14),
2. 5907517 - Memory circuit yield generator and timing adjustor (1999-05-25),
3. 5870346 - VLSI memory circuit (1999-02-09),
4. 5812461 - Driver circuit for addressing core memory and a method for the same (1998-09-22),
5. 5793698 - Semiconductor read-only VLSI memory (1998-08-11),
6. 5732035 - Very large scale integrated planar read only memory (1998-03-24),
7. 5650979 - Semiconductor read-only VLSI memory (1997-07-22),
8. 5608687 - Output driver control for ROM and RAM devices (1997-03-04),
9. 5596544 - Very large scale integrated planar read only memory (1997-01-21),
10. 5594696 - Improvemetns in a detection circuit with a level shifting circuit (1997-01-14),
11. 5581203 - Semiconductor read-only VLSI memory (1996-12-03),
12. 5487038 - Method for read cycle interrupts in a dynamic read-only memory (1996-01-23),
13. 5467300 - Grounded memory core for Roms, Eproms, and EEpproms having an address (1995-11-14),
14. 5459693 - Very large scale integrated planar read only memory (1995-10-17),
15. 5414663 - VLSI memory with an improved sense amplifier with dummy bit lines for (1995-05-09),

Title: The Inventor Profile of Clarence W Padgett

Introduction: Clarence W Padgett is a prolific inventor based in Westminster, California. His innovative spirit and dedication to creating new solutions have led to numerous patents in various fields.

Latest Patents: Clarence W Padgett's latest patents include groundbreaking inventions in the automotive industry, particularly focusing on eco-friendly technologies and safety enhancements.

Career Highlights: Throughout his career, Clarence W Padgett has been recognized for his contributions to the field of engineering, with a strong emphasis on sustainable practices. His inventions have not only improved existing technologies but have also paved the way for future advancements.

Collaborations: Clarence W Padgett has collaborated with leading research institutions and automotive companies to bring his inventions to life. His ability to work in multidisciplinary teams has resulted in successful projects that have had a significant impact on the industry.

Conclusion: Clarence W Padgett's passion for innovation and his commitment to creating a better future through his inventions make him a standout figure in the world of engineering. His work continues to inspire others to push the boundaries of what is possible in the field of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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