Grounded memory core for roms, eproms, and eepproms having an address

Abstract

The invention is an improved bank select read only memory in which the bit lines and virtual ground lines are all precharged to ground instead of being precharged to an internal low supply voltage. Both of the two virtual ground lines are selected for the selected bit and both selected virtual ground lines are driven to ground during the precharge phase. At the top of the memory array, all virtual ground lines in the memory array are precharged to ground during the precharge phase. Next during the sensing phase, the operation of the two virtual ground lines for the selected bit is changed to selectively hold one virtual ground line at ground and switch the second virtual ground line to a positive voltage. All bit lines are precharged to ground during the precharge phase. In the following sensing phase, the selected bit line is driven positive by the selected memory core FET if it is programmed with a low threshold voltage. If the selected memory core FET is programmed with a high threshold voltage, the bit line remains floating at the ground level, or it may be held at ground by means of the second virtual ground line, which is held at ground, and by low threshold core FETs, adjacent to the selected core FET, which are connected to the selected word line.