Memory circuit yield generator and timing adjustor

Abstract

Incremental values of a plurality of capacitors are programmably coupled through ROM core FETs with selective threshold voltages, EPROM core FETs, RAM cells, ROM fuse links or antifuse ROM links to a dummy bit line. The dummy bit line carries a bit line voltage to simulate either the worst case logical one or worst case logical zero within a read-only memory array of memory cells. The dummy bit line voltage is used as a control signal to a trigger circuit. The trigger circuit generates at the appropriate threshold a triggering signal used to control sense amplifiers coupled to the memory circuit. Therefore, by programmably altering the delay time on the dummy bit line, the read cycle of the memory can be programmably altered to either minimize the read time cycle to provide a fast, high quality memory product, or to maximize the read time cycle to provide for a slower but higher yield memory product at less expense.