The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 1996

Filed:

May. 05, 1995
Applicant:
Inventors:

James A Komarek, Balboa Beach, CA (US);

Scott B Tanner, Irvine, CA (US);

Clarence W Padgett, Westminster, CA (US);

Jack L Minney, Irvine, CA (US);

Assignee:

Creative Integrated Systems, Inc., Santa Ana, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03H / ;
U.S. Cl.
CPC ...
327-3 ; 327252 ; 327530 ;
Abstract

The performance of a very large scale integrated READ ONLY MEMORY circuit is improved by improvements in various circuits and methodologies utilized in the memory. Appropriate bias levels are generated by a bias circuit for use in the output buffer according to whether a process temperature and voltage variations within the memory circuit are such that variation sensitive components will be slowed upon the occurrence of such variations. The bias circuit otherwise generates a bias signal appropriate for fast speed operations within the output buffer circuit when process temperature and voltage variations are such that they do not effect circuit speed of sensitive circuit portions. The back bias generator which operates asynchronously from the memory cycle is improved by disabling the charge pumping action during a memory cycle.


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