Taipei, Taiwan

Chung-Che Tsai

This inventor holds 17 USPTO granted patents and 1 published patent application and 1 EPO patent, primarily in Semiconductor Packaging. Top assignees: Ultratera Corporation, United Test Center Inc., Other. Active years: 2001-2022.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chung-Che Tsai. Retrieved from https://idiyas.com/inventor/chung-che-tsai

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 17 

% Patents Active = 64.7

 

Average Co-Inventor Count = 1.7

ph-index = 7

Forward Citations = 248(Granted Patents)


Location History:

  • Hsinchu, TW (2004 - 2005)
  • Taipei, TW (2001 - 2022)

Company Filing History:


Years Active: 2001-2022

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Areas of Expertise:
Semiconductor Package
Fabrication Method
Heat Dissipation
Electro-Magnetic Compatibility
Circuit Board
Thermally Enhanced
Stacked Chip Package
Compartmental Shielding
Low Profile
Mold Structure
Bonding Pads
Multi-Chip
17 patents (USPTO):Explore Patents

Title: The Innovative Mind of Chung-Che Tsai: A Pioneer in Semiconductor Packaging

Introduction: Chung-Che Tsai, an accomplished inventor based in Taipei, TW, has made significant strides in the field of semiconductor packaging. With a remarkable portfolio of 17 patents, his inventions are at the forefront of technology, addressing critical challenges in the industry.

Latest Patents: Among his latest contributions, Tsai developed a semiconductor package and fabrication method that includes a substrate with a high-frequency chip and circuit components. This innovative package features several critical elements: a ground pad positioned between the high-frequency chip and circuit component, a metal-post reinforced glue wall on the ground pad, and a molding compound that surrounds both the glue wall and the chips. This design ensures that the root mean square (RMS) roughness between the base of the metal posts and the ground pad is less than 1.0 micrometer, enhancing signal integrity.

Another notable patent is a semiconductor package equipped with in-package compartmental shielding and active electromagnetic compatibility. This package includes a substrate that houses a semiconductor chip, surrounded by a ground ring and a metal-post reinforced glue wall. The addition of a magnetic or magnetizable filler provides active electromagnetic compatibility shielding, further demonstrating Tsai's innovative approach to semiconductor design.

Career Highlights: Tsai has had a diverse career, significantly contributing to advancements in semiconductor technologies. Notably, he worked with Ultratera Corporation, where he applied his expertise to develop cutting-edge solutions that have impacted the semiconductor market.

Collaborations: Throughout his career, Tsai has collaborated with noteworthy individuals in the field, including Wei-Heng Shan and Hsien-Chou Tsai. These partnerships have facilitated the exchange of ideas and fostered innovation within the semiconductor sector.

Conclusion: Chung-Che Tsai's work exemplifies the spirit of innovation in semiconductor packaging. His extensive patent portfolio not only illustrates his technical prowess but also contributes to the ongoing evolution of technology in this critical field. As he continues to push the boundaries of invention, Tsai remains a key figure in the world of semiconductor innovation.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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