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For the Inventor, By the Inventor

Kaohsiung, Taiwan

Chun Hung Lin

This inventor holds 15 USPTO granted patents. Top assignees: Advanced Semiconductor Engineering, Inc., Other. Active years: 2001-2004.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chun Hung Lin. Retrieved from https://idiyas.com/inventor/chun-hung-lin-1i3d71oc

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 15

% Patents Active = 100.0

Average Co-Inventor Count = 1.8

ph-index = 13

Forward Citations = 613(Granted Patents)


Company Filing History:

goldMedal14 out of 1,964 
 
Advanced Semiconductor Engineering, Inc.
 patents
silverMedal1 out of 834,513 
Other
 patents

Years Active: 2001-2004

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15 patents (USPTO):Explore Patents
1. 6700188 - Low-pin-count chip package having concave die pad and/or connections pads (2004-03-02),
2. 6573123 - Semiconductor chip package and manufacturing method thereof (2003-06-03),
3. 6534852 - Ball grid array semiconductor package with improved strength and electric performance and method for making the same (2003-03-18),
4. 6461897 - Multichip module having a stacked chip arrangement (2002-10-08),
5. 6455353 - Method of making semiconductor packages at wafer level (2002-09-24),
6. 6413801 - Method of molding semiconductor device and molding die for use therein (2002-07-02),
7. 6359340 - Multichip module having a stacked chip arrangement (2002-03-19),
8. 6348729 - Semiconductor chip package and manufacturing method thereof (2002-02-19),
9. 6348399 - Method of making chip scale package (2002-02-19),
10. 6338813 - Molding method for BGA semiconductor chip package (2002-01-15),
11. 6333562 - Multichip module having stacked chip arrangement (2001-12-25),
12. 6312976 - Method for manufacturing leadless semiconductor chip package (2001-11-06),
13. 6252305 - Multichip module having a stacked chip arrangement (2001-06-26),
14. 6238952 - Low-pin-count chip package and manufacturing method thereof (2001-05-29),
15. 6204559 - Ball grid assembly type semiconductor package having improved chip edge support to prevent chip cracking (2001-03-20),

Title: Innovations of Chun Hung Lin

Introduction

Chun Hung Lin is a prominent inventor based in Kaohsiung, Taiwan. He has made significant contributions to the field of semiconductor packaging, holding a total of 15 patents. His work focuses on innovative designs that enhance the functionality and efficiency of semiconductor chip packages.

Latest Patents

One of his latest patents is titled "Low-pin-count chip package having concave die pad and/or connections pads." This invention features a low-pin-count chip package that includes a die pad for receiving a semiconductor chip and multiple connection pads that are electrically coupled to the chip. The unique aspect of this design is that both the die pad and the connection pads have a concave profile. The package body is formed over the semiconductor chip, die pad, and connection pads, allowing portions of these components to extend outward from the bottom of the package body. Additionally, he has developed a patent for a "Semiconductor chip package and manufacturing method thereof." This invention comprises a lead frame, a semiconductor die, and a plastic package body, with a design that ensures the semiconductor die is securely encapsulated while maintaining accessibility to critical components.

Career Highlights

Chun Hung Lin has worked with Advanced Semiconductor Engineering, Inc., where he has contributed to various projects that focus on semiconductor technology. His expertise in this field has allowed him to develop innovative solutions that address industry challenges.

Collaborations

Throughout his career, Chun Hung Lin has collaborated with notable colleagues, including Su Tao and Kuang-Hui Chen. These partnerships have fostered a creative environment that has led to the development of groundbreaking technologies in semiconductor packaging.

Conclusion

Chun Hung Lin's contributions to semiconductor packaging through his innovative patents and collaborations highlight his significant role in advancing technology in this field. His work continues to influence the industry and pave the way for future innovations.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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