Advanced Semiconductor Engineering, Inc.

Other

Chun Hung Lin

Su Tao

Kuang-Hui Chen

Shyh-Wei Wang

Shin Hua Chao

Jian Wen Chen

Sai Man Li

Chun-Chi Lee

Kun-Ching Chen

Kao-Yu Hsu

Tao-Yu Chen

I Zeng Lee

Yire Zine Lee

A low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip wherein the die pad and the connection pads have a concave profile. A package body is formed over the semiconductor chip, the die pad and the connection pads in a manner that a potion of the die pad and a portion of each connection pad extend outward from the bottom of the package body. The present invention further provides a novel method of producing the low-pin-count chip package described above.

Low-pin-count chip package having concave die pad and/or connections pads

A semiconductor chip package generally comprises a lead frame, a semiconductor die and a plastic package body. The lead frame includes a plurality of leads and a window pad. The window pad is connected to the lead frame by connecting bars. The inner ends of the plurality of leads defines a central area. The window pad is disposed in the central area and has an opening defined therein. The semiconductor die is disposed in the opening of the window pad and has a plurality of bonding pads formed on the active surface thereof. The inner ends of the leads are interconnected to the bonding pads on the semiconductor die through a plurality of bonding wires. The lead frame, the semiconductor die and the bonding wires are encapsulated in the plastic package body wherein the lower surface of the lead frame and the backside surface of the semiconductor die are exposed through the plastic package body.

Semiconductor chip package and manufacturing method thereof

Disclosed are metal reinforced layers disposed at the upper and lower surfaces of the thin substrate to reinforce the strength of the thin substrate. With reinforced strength, the thin substrate is not susceptible to deform due to temperature fluctuation during packaging process, and thus the warpage for the semiconductor package is significantly eliminated. According to another aspect of the present invention, the metal reinforced layer at the lower surface of the thin substrate is functioned as a ground plane for the ball grid array (BGA) semiconductor package for better grounding effect. The present invention provides an optimal design for the return current path and impedance matching control. Besides, in high frequency application, the metal reinforced layer also can reduce the noise and cross talk among the signal lines of the ball grid array (BGA) semiconductor package.

Ball grid array semiconductor package with improved strength and electric performance and method for making the same

A multichip module comprises at least two semiconductor chips wherein each has a row of bonding pads formed on the active surface thereof and disposed along one side edge thereof. The semiconductor chips are mounted to a substrate in a stacking arrangement wherein the upper chip is attached to the active surface of the lower chip in a manner that no portion of the upper chip interferes with a vertical line of sight of each bond pad of the lower chip to permit wire bonding thereof. Therefore, all semiconductor chips can be wire bonded simultaneously after stacking the chips on the substrate. This allows wire bonding of all chips to be completed in a single step so as to increase UPH (unit per hour), thereby reducing cost for manufacturing the MCM.

Multichip module having a stacked chip arrangement

A method of manufacturing chip scale packages at wafer level, comprising the steps of: a) providing a wafer having an active and a back side surface, the active surface of the wafer having a plurality of scribe lines defining individual chips, and each chip having a plurality of electrodes; b) forming a dam enclosing the perimeter of the wafer; c) filling the area enclosed by the dam with molding compound to encapsulate the active surface of the wafer; d) removing the dam to expose the scribe lines covered by the dam on the active surface of the wafer; and e) dicing the wafer according to the exposed scribe lines as positioning reference marks.

Method of making semiconductor packages at wafer level

A method of molding a semiconductor device comprising the steps of: (a) providing a molding die comprising a molding portion having a cavity for accepting the semiconductor device, a dummy cavity connected to the cavity and an air vent connected to the dummy cavity; (b) closing and clamping the molding die in a manner that the semiconductor chip is positioned in the cavity; (c) transferring a molding material into the cavity and the dummy cavity; (d) hardening the molding material; (e) unclamping and opening the molding die to take out the molded product. The molding method of the present invention is characterized in that even though the cavity with the semiconductor device positioned therein is filled, the transfer ram keeps moving such that the molding material is forced to continue flowing into the dummy cavity. This invention further provides a molding die for use in molding a semiconductor device. The molding die mainly comprises a pot for storing molding material, a molding portion and a runner. The molding portion has a cavity for accepting the semiconductor device, a dummy cavity connected to the cavity and an air vent connected to the dummy cavity. The runner has one end connected to the pot and the other end connected to the cavity through a gate. The channel for connecting the cavity to the dummy cavity has a size substantially the same as the size of the gate such that during molding, the molding material will fill the cavity through the runner and the gate, and then fill the dummy cavity through the channel.

Method of molding semiconductor device and molding die for use therein

A multichip module has at least two semiconductor chips wherein each has a row of bonding pads formed on the active surface thereof and disposed along one side edge thereof. In some embodiments, the semiconductor chips may have a plurality of bonding pads along only two mutually perpendicular side edges thereof. The semiconductor chips are mounted to a substrate in a stacking arrangement wherein the upper chip is attached to the active surface of the lower chip in a manner that no portion of the upper chip interferes with a vertical line of sight of each bonding pad of the lower chip to permit wire bonding thereof. Therefore, all semiconductor chips can be wire bonded simultaneously after stacking the chips on the substrate. This allows wire bonding of all chips to be completed in a single step so as to increase UPH (unit per hour), thereby reducing cost for manufacturing the MCM.

A method of making a chip scale package comprises the following steps: providing a semiconductor chip having a plurality of metal bumps formed on the active surface thereof; providing a metal plate having a plurality of flip-chip pads formed on a surface thereof; positioning the semiconductor chip on the surface of the metal plate with the metal bumps on the chip aligned with the flip-chip pads on the metal plate; connecting the metal bumps on the active surface of the semiconductor chip to the flip-chip pads on the surface of the metal plate; encapsulating the semiconductor chip against a portion of the surface of the metal plate; removing the metal plate while leaving the flip-chip pads intact; and forming a plurality of solder balls on the flip-chip pads. Using the technique of the present invention, it becomes possible that the manufacture of a molded chip scale package can be relatively simplified and economical, yet highly reliable.

Method of making chip scale package

A molding method for a BGA semiconductor chip package comprising a substrate supporting an array of chips having two lines of bonding pads formed at two respective side thereof. The molding method comprises the steps of: (A) providing a molding apparatus comprising a molding die having a molding cavity and at least two runners connected to the molding cavity; (B) closing and clamping the molding die in a manner that the chips are located in the molding cavity thereof; (C) transferring a molding compound into the molding cavity wherein each chip is arranged in a manner that the two lines of bonding pads thereof are substantially perpendicular to the flowing direction of the molding compound; (D) curing the molding compound; and (E) unclamping and opening the molding die to take out the molded product.

Molding method for BGA semiconductor chip package

A multichip module mainly comprises two stacked chips disposed on and respectively wire bonded to a substrate or a lead frame. There are a plurality of electrically conductive bumps having base portions and pillar protruding portions interposed between the two chips. The conductive bumps are attached at their base portions to the bonding pads of the lower chip and connected at their pillar protruding portions to the backside surface of the upper chip so as to support the upper chip. In the multichip module of the present invention, the pillar protruding portions of bumps help to provide clearance between the two chips for keeping the upper chip from damaging the bonding wires of the lower chip.

Multichip module having stacked chip arrangement

A method of manufacturing a leadless semiconductor chip package comprises the steps of: attaching a semiconductor die onto a die pad of a lead frame, wherein the lead frame comprises a plurality of leads arranged about the periphery of the die pad and each lead has a notch formed at the to-be-punched position thereof; wire bonding the inner ends of the leads to bonding pads on the semiconductor die; sucking a film against a lower part of a molding die; closing and clamping the molding die in a manner that the semiconductor die is positioned in a cavity of the molding die and the lead frame is disposed against the film; transferring a hardenable molding compound into the cavity; hardening the molding compound; opening the molding die to take out the molded product; and punching the molded product along the notches of the leads thereby making the singulation process more convenient and correct. The lower surface of each lead of the lead frame according to the present invention is smaller than the upper surface thereof such that each lead has a tapered profile which cooperates with the film to provide better sealing effect thereby preventing the formation of flash.

Method for manufacturing leadless semiconductor chip package

Low-pin-count chip package and manufacturing method thereof

This invention moves at least one outer via outwardly to a location under the edge of the chip so as to form an offset via. Since the via is made of copper, the offset via provides sufficient supporting strength for the chip edge during molding process. Further, this invention also disposes a copper mesh on the substrate at the area without vias and traces so as to enhance the substrate strength for supporting the chip. According to another aspect of this invention, dummy via holes are provided for the substrate at the area under the chip edge for supporting the chip. Since the copper mesh, offset via, the dummy via hole are made of copper having sufficient supporting strength for the chip, the crack problem during molding process can be eliminated.

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Kaohsiung, Taiwan

Chun Hung Lin