This inventor holds 5 USPTO granted patents and 1 EPO patent. Top assignees: Synopsys, Inc., Cadence Design Systems, Inc.. Active years: 2012-2023.
Location History:
- Saratoga, CA (US) (2012 - 2020)
- Mountain View, CA (US) (2021 - 2023)
Company Filing History:
Years Active: 2012-2023
Title: Ching-Ping Chou: Innovator in Hardware Verification
Introduction
Ching-Ping Chou is a notable inventor based in Saratoga, CA (US). He has made significant contributions to the field of hardware verification, holding a total of 5 patents. His work primarily focuses on methods that enhance the efficiency and effectiveness of circuit design verification.
Latest Patents
One of Ching-Ping Chou's latest patents is a method for capturing signals during hardware verification of a circuit design. This innovative approach utilizes at least one field-programmable gate array (FPGA). The method includes selecting, at run time and using one or more pre-compiled macros, a group of signals to be captured during the verification process. The values of these signals are stored in at least first and second random access memories within the FPGA. Notably, the first and second random access memories may be addressable spaces of the same random access memory.
Career Highlights
Ching-Ping Chou has worked with prominent companies in the technology sector, including Synopsys, Inc. and Cadence Design Systems, Inc. His experience in these organizations has allowed him to refine his skills and contribute to groundbreaking advancements in hardware verification.
Collaborations
Ching-Ping has collaborated with talented individuals in his field, including Arturo Salz and Jean-Philippe Colrat. These partnerships have fostered innovation and have been instrumental in the development of his patented technologies.
Conclusion
Ching-Ping Chou's contributions to hardware verification through his patents and collaborations highlight his role as a significant innovator in the field. His work continues to influence the way circuit designs are verified, ensuring greater efficiency and reliability in technology development.