The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 16, 2021
Filed:
Nov. 10, 2017
Synopsys, Inc., Mountain View, CA (US);
Arturo Salz, Menlo Park, CA (US);
Ching-Ping Chou, Mountain View, CA (US);
Jean-Philippe Colrat, Mountain View, CA (US);
Sébastien Roger Delerse, Mountain View, CA (US);
Luc François Vidal, Mountain View, CA (US);
Arnold Mbotchak, Mountain View, CA (US);
SYNOPSYS, INC., Mountain View, CA (US);
Abstract
A method of capturing signals during hardware verification of a circuit design utilizes at least one field-programmable gate array (FPGA) and includes selecting, at run time and using one or more pre-compiled macros, a group of signals to be captured during verification of the circuit design and storing values of the group of signals in at least first and second random access memories disposed in the at least one FPGA. The first and second random access memories may be addressable spaces of the same random access memory.