Austin, TX, United States of America

Chih-Jen M Lin

This inventor holds 5 USPTO granted patents. Top assignee: Intel Corporation. Active years: 2003-2011.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chih-Jen M Lin. Retrieved from https://idiyas.com/inventor/chih-jen-m-lin

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 60.0

Average Co-Inventor Count = 2.8

ph-index = 3

Forward Citations = 47(Granted Patents)


Company Filing History:


Years Active: 2003-2011

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5 patents (USPTO):Explore Patents

Title: Innovations of Chih-Jen M Lin

Introduction

Chih-Jen M Lin is a prominent inventor based in Austin, TX, known for his contributions to the field of system-on-chip design. He has been awarded a total of 5 patents throughout his career, showcasing his innovative approach to technology.

Latest Patents

One of his latest patents is titled "Scalable scan system for system-on-chip design." This invention presents a method and system that facilitates a scalable scan system in the design of a system-on-chip. In one embodiment, the system-on-chip includes a controller and one or more clock gating units. The clock gating unit is added to each unique clock domain of each function or logic block in the system-on-chip. By having a controller that connects to each clock gating unit and the scan input and output signals in each logic block of the SOC, this allows a scalable scan system in the design of the SOC. It also enables frequent block-level design changes in the SOC without extensive modifications to the scan logic. Additionally, the scalable scan system allows at-speed scan write-through testing of a memory array, which can improve the scan test coverage of the system-on-chip.

Another significant patent is the "Method and apparatus for testing a memory array." This technique focuses on testing a memory array within a device under test (DUT) at speeds similar to those under typical operating conditions. This approach minimizes die real estate and power penalties, making it a valuable contribution to memory testing architecture.

Career Highlights

Chih-Jen M Lin is currently employed at Intel Corporation, where he continues to innovate and develop cutting-edge technologies. His work has significantly impacted the efficiency and effectiveness of system-on-chip designs.

Collaborations

Throughout his career, Chih-Jen has collaborated with notable colleagues, including David M Wu and Nguyen N Ngo. These partnerships have further enhanced his contributions to the field.

Conclusion

Chih-Jen M Lin's innovative work in system-on-chip design and memory testing has established him as a key figure in the technology sector. His patents reflect a commitment to advancing the capabilities of electronic devices, making a lasting impact on the industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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