Intel Corporation

Chih-Jen M Lin

David M Wu

Wei Ey Li

Larry Edward Thatcher

Srinivas Patil

Talal K Jaber

Anil K Sabbavarapu

Nguyen N Ngo

Praveen Sathyanarayanan

Zhuoyu Bao

Madhukar K Reddy

A method and system to facilitate a scalable scan system in the design of a system-on-chip. In one embodiment of the invention, the system-on-chip includes a controller and one or more clock gating units. The clock gating unit is added to each unique clock domain of each function or logic block in the system-on-chip. By having a controller that connects to each clock gating unit and the scan input and output signals in each logic block of the SOC, this allows a scalable scan system in the design of the SOC and allows frequent block level design changes in the SOC without extensive changes to the scan logic in one embodiment of the invention. In addition, the scalable scan system also allows at-speed scan write-through testing of a memory array that can improve the scan test coverage of the system-on-chip.

Scalable scan system for system-on-chip design

A technique for testing a memory array. More particularly, embodiments of the invention relate to a memory array testing architecture in which a memory array within a device under test (DUT) is able to be tested at speeds substantially similar to those under typical operating conditions of the memory array without incurring significant die real estate and power penalties.

Method and apparatus for testing a memory array

A testing architecture for testing a complex integrated circuit in which each functional unit may be tested independently of the others. Embodiments of the invention allow testing of functional units to take place at slower or faster clock speeds than other portions of the processor without incurring delay or other adverse timing effects.

Flexible scan architecture

An apparatus and method of testing an integrated circuit by downloading a sequence of randomly weighted bits into a scan chain in which each bit has a distinctly determined weight generated in real-time by a weight generator. The weight generator has a switch controlled by a stored bit particular for each bit of the randomly weighted bits that determines the weight of the bit. The control signal is stored in a memory that is downloaded into the switch in synchronization with the generation of the bit. Preferably, the memory is on-die, and furthermore is a part of the integrated circuit.

Weighted random pattern test using pre-stored weights

Improved apparatus and methods for performing programmable built-in self-testing (PBIST) of memory serve to capture failure information while minimizing the silicon area used for implementation. Rather than saving all data subsequent to the first detection of a memory failure, on-chip storage elements save command, address, and program counter values corresponding to the instruction generating the first memory failure as well as to a number of subsequent instructions, but only a single memory block of data values is saved. The total silicon area of the elements that store the command, address, program counter, and data values is significantly less than that required to save all data corresponding to the first and subsequent faulty read operations. Methods of operation, as well as application of the apparatus to an electronic assembly, an electronic system, and a data processing system, are also described.

Growing community of inventors

Austin, TX, United States of America

Chih-Jen M Lin