Chien-Chuan Wei

This inventor holds 25 USPTO granted patents and 3 published patent applications, primarily in Semiconductor Packaging. Top assignees: Marvell International Limited, Marvellworld Trade Ltd.. Active years: 2010-2017.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chien-Chuan Wei. Retrieved from https://idiyas.com/inventor/chien-chuan-wei

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

USPTO Granted Patents = 25 (Patent Applications = 3)

% Patents Active = 36.0

Average Co-Inventor Count = 4.1

ph-index = 5

Forward Citations = 78(Granted Patents)

Location History:

Sunnyvale, CA (US) (2010 - 2015)
Los Gatos, CA (US) (2013 - 2016)
San Diego, CA (US) (2016 - 2017)

Company Filing History:

15 out of 5,162

Marvell International Limited

patents

10 out of 1,901

Marvellworld Trade Ltd.

patents

Years Active: 2010-2017

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Areas of Expertise:

Semiconductor Substrate

Recessed Region

Transistor Pitch

Photo-Resist Material

High-Density Patterning

Alpha Shielding

Contact Holes

Phase Change Memory

Bipolar Junction Transistor

Metal Interconnects

Heater Trenches

Ion Implantation

25 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 9768144 - Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate (2017-09-19),

2. 9391045 - Recessed semiconductor substrates and associated techniques (2016-07-12),

3. 9275929 - Package assembly having a semiconductor substrate (2016-03-01),

4. 9257410 - Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate (2016-02-09),

5. 9245961 - Reducing source contact to gate spacing to decrease transistor pitch (2016-01-26),

6. 9034730 - Recessed semiconductor substrates and associated techniques (2015-05-19),

7. 8999786 - Reducing source contact to gate spacing to decrease transistor pitch (2015-04-07),

8. 8753976 - Methods and apparatus for etching photo-resist material through multiple exposures of the photo-resist material (2014-06-17),

9. 8609528 - High-density patterning (2013-12-17),

10. 8603861 - Alpha shielding techniques and configurations (2013-12-10),

11. 8501619 - Methods for forming a plurality of contact holes in a microelectronic device (2013-08-06),

12. 8368214 - Alpha shielding techniques and configurations (2013-02-05),

13. 8030128 - Method to form high density phase change memory (PCM) top contact every two bits (2011-10-04),

14. 8003523 - Methods for forming a plurality of contact holes in a microelectric device (2011-08-23),

15. 7994052 - High-density patterning (2011-08-09),

Title: The Innovative Journey of Chien-Chuan Wei

Introduction: Chien-Chuan Wei, a talented inventor based in Sunnyvale, CA, has made significant contributions to the field of technology through his groundbreaking innovations.

Latest Patents: Chien-Chuan Wei's latest patents focus on advancements in artificial intelligence and renewable energy technologies, showcasing his commitment to creating a more sustainable future.

Career Highlights: With a background in engineering and a passion for problem-solving, Chien-Chuan Wei has led successful projects in the development of cutting-edge software and hardware solutions for various industries.

Collaborations: Throughout his career, Chien-Chuan Wei has collaborated with leading tech companies and research institutions to bring his ideas to life, fostering a culture of innovation and creativity.

Conclusion: Chien-Chuan Wei's dedication to pushing the boundaries of technology and his relentless pursuit of excellence make him a true pioneer in the world of inventions.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

3 patents pending: