The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 09, 2016
Filed:
Jan. 24, 2011
Albert Wu, Palo Alto, CA (US);
Roawen Chen, Monte Sereno, CA (US);
Chung Chyung Han, San Jose, CA (US);
Shiann-ming Liou, Campbell, CA (US);
Chien-chuan Wei, Los Gatos, CA (US);
Runzi Chang, San Jose, CA (US);
Scott Wu, San Jose, CA (US);
Chuan-cheng Cheng, Fremont, CA (US);
Albert Wu, Palo Alto, CA (US);
Roawen Chen, Monte Sereno, CA (US);
Chung Chyung Han, San Jose, CA (US);
Shiann-Ming Liou, Campbell, CA (US);
Chien-Chuan Wei, Los Gatos, CA (US);
Runzi Chang, San Jose, CA (US);
Scott Wu, San Jose, CA (US);
Chuan-Cheng Cheng, Fremont, CA (US);
Marvell World Trade Ltd., St. Michael, BB;
Abstract
Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed.