The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2015
Filed:
Jan. 28, 2011
Albert Wu, Palo Alto, CA (US);
Roawen Chen, Monte Sereno, CA (US);
Chung Chyung Han, San Jose, CA (US);
Shiann-ming Liou, Campbell, CA (US);
Chien-chuan Wei, Los Gatos, CA (US);
Runzi Chang, San Jose, CA (US);
Scott Wu, San Jose, CA (US);
Chuan-cheng Cheng, Fremont, CA (US);
Albert Wu, Palo Alto, CA (US);
Roawen Chen, Monte Sereno, CA (US);
Chung Chyung Han, San Jose, CA (US);
Shiann-Ming Liou, Campbell, CA (US);
Chien-Chuan Wei, Los Gatos, CA (US);
Runzi Chang, San Jose, CA (US);
Scott Wu, San Jose, CA (US);
Chuan-Cheng Cheng, Fremont, CA (US);
Marvell World Trade Ltd., St. Michael, BB;
Abstract
Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed.