Chieh-Yu Lin

Title: Innovations of Chieh-Yu Lin

Introduction

Chieh-Yu Lin is a prominent inventor based in Hopewell Junction, NY (US). He holds a total of 11 patents, showcasing his significant contributions to the field of semiconductor technology. His work primarily focuses on optimizing design for manufacturability in semiconductor fabrication.

Latest Patents

One of his latest patents involves a method for semiconductor fabrication design rule loophole checking for design for manufacturability optimization. This technical solution describes the process of fabricating a semiconductor wafer. The method includes generating a process assumption band for an element of the wafer, which depicts the shape of the element based on a set of process variations in a photolithographic process. Additionally, it involves generating a process variation band for the element based on optical process correction simulation using design rules associated with the wafer. The method also determines a deviation between the process assumption band and the process variation band, recalculates design rules based on this deviation, and updates the wafer design accordingly.

Career Highlights

Chieh-Yu Lin has worked with notable companies such as IBM and STMicroelectronics GmbH. His experience in these organizations has allowed him to develop and refine his innovative approaches to semiconductor fabrication.

Collaborations

Some of his coworkers include Kehan Tian and Wai-Kin Li, who have collaborated with him on various projects in the semiconductor field.

Conclusion

Chieh-Yu Lin's contributions to semiconductor technology through his patents and collaborations highlight his role as a key innovator in the industry. His work continues to influence the optimization of semiconductor fabrication processes.