The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 15, 2021

Filed:

Jun. 14, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Chieh-Yu Lin, Hopewell Junction, NY (US);

Dongbing Shao, Wappingers Falls, NY (US);

Kehan Tian, Poughkeepsie, NY (US);

Zheng Xu, Wappingers Falls, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/33 (2020.01); G03F 1/36 (2012.01); G03F 1/70 (2012.01); G03F 1/38 (2012.01); G06F 30/20 (2020.01); G06F 30/398 (2020.01); G06F 119/18 (2020.01);
U.S. Cl.
CPC ...
G03F 1/36 (2013.01); G03F 1/38 (2013.01); G03F 1/70 (2013.01); G06F 30/20 (2020.01); G06F 30/398 (2020.01); G06F 2119/18 (2020.01);
Abstract

Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.


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