International Business Machines Corporation

Stmicroelectronics Gmbh

Globalfoundries Inc.

Samsung Electronics Co., Ltd.

Infineon Technologies Ag

Chieh-Yu Lin

Kehan Tian

Zheng Xu

Wai-Kin Li

Dongbing Shao

Yannick Daurelle

Mark Alan Lavin

Fook-Luen Heng

Rama Nand Singh

Jawahar P Nayak

Jin-Fuw Lee

Maharaj Mukherjee

Kafai Lai

Sanghoon Baek

Zhijian Lu

Nayak Jawahar

Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.

Semiconductor fabrication design rule loophole checking for design for manufacturability optimization

A semiconductor device includes a plurality of gates formed upon a semiconductor substrate that includes a plurality of outer active areas (e.g. CMOS/PMOS areas, source/drain regions, etc.) and one or more inner active areas. An isolator is formed upon one or more inner gates associated with the one or more inner active areas. A contact bar electrically connects the outer active areas and/or outer gates and is formed upon the isolator. The isolator electrically insulates the contact bar from the one or more inner active areas and/or the one or more inner gates.

Bridging local semiconductor interconnects

A design layout includes a set of active region-level design shapes representing semiconductor active regions, and a set of gate-level design shapes representing gate lines straddling the semiconductor active regions. The set of gate-level design shapes include a sub-resolution assist feature (SRAF) that connects two gate-level design shapes, and is physically manifested as a gap between two gate lines upon printing employing lithographic methods. An edge of a gate line in proximity to a semiconductor active region can be cut employing a cut mask that includes a cut-level design shape that has a protruding tap. The protruding tap allows reliable removal of an end portion of a gate line and prevents disruption of raised source and drain regions by an unwanted residual gate structure.

High density field effect transistor design including a broken gate line

A system and method of employing patterning process statistics to evaluate layouts for intersect area analysis includes applying Optical Proximity Correction (OPC) to the layout, simulating images formed by the mask and applying patterning process variation distributions to influence and determine corrective actions taken to improve and optimize the rules for compliance by the layout. The process variation distributions are mapped to an intersect area distribution by creating a histogram based upon a plurality of processes for an intersect area. The intersect area is analyzed using the histogram to provide ground rule waivers and optimization.

System and method for employing patterning process statistics for ground rules waivers and optimization

A method is described for computing distance based and pattern density based design rules for the mask layout design of a VLSI chip so that the design satisfying the above design rules when manufactured on a wafer do not violate the specified tolerance on the critical dimensions (CD). The design rules are developed on the computed enclosed energy which is a convolution of the total optical energy and the pattern density of the mask. The total optical energy is the sum of the short range diffraction limited optical energy and the long range optical flare. The method steps for generating rules for a mask layout include: selecting a mask shape from a plurality thereof inputted from the mask layout, and determining a CD of the selected mask shape and a tolerance on variations of the CD; building a physical model of a component of the energy contributed by surrounding regions at a predetermined distance from the CD; using the physical model, computing the energy enclosed within the surrounding regions at the predetermined distance, and the maximum pattern density there of while remaining within the tolerance on variations of the CD; and outputting the maximum pattern density as a rule for the surrounding region at that distance.

Method for generating design rules for a lithographic mask design that includes long range flare effects

A method of transferring a pattern onto a substrate, in the fabrication of ICs, is disclosed. The substrate is coated with a photoresist layer, wherein the photoresist layer is selectively exposed and developed, producing sidewalls that exhibit roughness. The roughness is smoothened out by coating the photoresist layer with a coating layer.

Pattern transfer in device fabrication

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Hopewell Junction, NY, United States of America

Chieh-Yu Lin