Keelung, Taiwan

Chia Cheng Chou

This inventor holds 20 USPTO granted patents and 5 published patent applications, primarily in Low-K Dielectric Technology. Top assignees: Taiwan Semiconductor Manufacturing Comp. Ltd., Other. Active years: 2000-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chia Cheng Chou. Retrieved from https://idiyas.com/inventor/chia-cheng-chou-uijk6jbo

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 20 

% Patents Active = 85.0

Average Co-Inventor Count = 3.5

ph-index = 3

Forward Citations = 72(Granted Patents)


Location History:

  • Hsintien, Taipei, Hsien, TW (2000)
  • Keelung, TW (2011 - 2024)

Company Filing History:


Years Active: 2000-2025

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Areas of Expertise:
Low-K Dielectric
Semiconductor Device
Interconnect Structure
Active Energy Assist Baking
Multi-Patterning
Oxidation Reduction
Via Formation
Chemical Integrity
20 patents (USPTO):Explore Patents

Title: Innovations of Chia Cheng Chou in Semiconductor Technology

Introduction

Chia Cheng Chou, located in Keelung, Taiwan, is a prominent inventor recognized for his significant contributions to the field of semiconductor technology. With a total of 19 patents to his name, Chou has demonstrated a commitment to advancing innovations in the processing and manufacturing of semiconductor devices.

Latest Patents

Among his latest inventions, one notable patent is the "Semiconductor device having an extra low-k dielectric layer and method of forming the same." This patent presents a comprehensive method for manufacturing an extra low-k dielectric layer, which is crucial for reducing capacitance in semiconductor structures. The process involves forming multiple dielectric material layers, establishing an adhesion layer, and subsequently creating an extra low-k dielectric layer. A protective layer and a hard mask are applied to define regions for the formation of metal layers, culminating in improved device performance.

Another significant contribution is the patent titled "Reducing oxidation by etching sacrificial and protection layer separately." This innovation addresses the structural design of conductive features within semiconductor devices, enhancing the durability and reliability of electronic components. The patent details the arrangement of conductive features and protective components, which help minimize oxidation and improve overall functionality.

Career Highlights

Chou has made substantial strides in the semiconductor industry through his role at the Taiwan Semiconductor Manufacturing Company (TSMC), where he has been actively involved in various groundbreaking projects. His work at TSMC has allowed him to influence several key processes in semiconductor manufacturing that have optimized product performance and efficiency.

Collaborations

Throughout his career, Chia Cheng Chou has collaborated with industry professionals including Po-Cheng Shih and Chung-Chi Ko. These collaborations have fostered a synergistic environment, leading to innovative solutions and advancements within the semiconductor sector.

Conclusion

Chia Cheng Chou's contributions to semiconductor technology and his extensive patent portfolio underscore his influence as an inventor in the field. His innovative approaches and collaborative efforts continue to pave the way for advancements that enhance the efficiency and effectiveness of semiconductor devices, affirming his status as a leading figure in this crucial industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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