Cambridge, MA, United States of America

Bradley A Burres

This inventor holds 31 USPTO granted patents and 13 published patent applications and 4 EPO patents, primarily in Data Storage Technologies. Top assignees: Intel Corporation, Sk Hynix Nand Product Solutions Corp.. Active years: 2006-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Bradley A Burres. Retrieved from https://idiyas.com/inventor/bradley-a-burres

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 31 

% Patents Active = 74.2

 

Average Co-Inventor Count = 5.4

ph-index = 7

Forward Citations = 170(Granted Patents)


Location History:

  • Cambridge, MA (US) (2006 - 2013)
  • West Newton, MA (US) (2018 - 2020)
  • Waltham, MA (US) (2010 - 2024)
  • Newton, MA (US) (2024)

Company Filing History:


Years Active: 2006-2026

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Areas of Expertise:
Data Storage
Virtualization
Cryptographic Processing
Media Streaming
SmartNIC
Dynamic Configuration
Memory Controllers
Multi-Core Communication
SATA Controller
Protocol Acceleration
Integrated Circuits
Cyclic Redundancy Check
31 patents (USPTO):Explore Patents

Title: The Innovative Contributions of Bradley A. Burres in Data Security and I/O Technology

Introduction

Bradley A. Burres is a prominent inventor based in Cambridge, MA, recognized for his significant contributions to the fields of data security and input/output (I/O) technology. With an impressive portfolio of 27 patents, Burres has consistently pushed the boundaries of innovation, particularly in virtual machine encryption and dynamic I/O configuration.

Latest Patents

One of Burres' latest inventions focuses on "VM encryption of block storage with end-to-end data integrity protection in a SmartNIC." This inventive method involves a Network Interface Card (NIC) that is equipped to encrypt data blocks during write operations. It appends these blocks with protection information generated using the data itself, creating a protected data block that is then forwarded over a network to a storage node. For read operations, the NIC identifies and validates protection information to ensure data integrity prior to decrypting and transmitting payload data to a host.

Additionally, Burres has developed technology for the "Dynamic configuration of input/output controller access lanes." This invention introduces systems and methods for the flexible configuration and enforcement of access lanes to I/O controllers, allowing for real-time adjustments based on detected change requests. The smart system can verify configurations against stock keeping units (SKUs) and, upon successful validation, can reset to accommodate new setups.

Career Highlights

Throughout his career, Burres has made substantial contributions while working for major technology companies such as Intel Corporation and SK Hynix NAND Product Solutions Corp. His ongoing commitment to innovation in both hardware and software is evidenced by his diverse patent portfolio, which reflects his expertise in creating solutions that enhance data security, performance, and efficiency.

Collaborations

Bradley A. Burres has collaborated with notable colleagues, including Gilbert M. Wolrich and Wajdi K. Feghali. Working alongside such talented individuals, Burres has been able to influence the technological landscape through shared insights and innovative ideas.

Conclusion

In conclusion, Bradley A. Burres stands out as a leading inventor in Cambridge, MA, whose developments in data encryption and I/O technology have made a significant impact on the industry. His 27 patents not only showcase his innovative spirit but also his dedication to enhancing data integrity and operational efficiency in technological systems. As he continues to create and innovate, Burres remains a vital contributor to the advancements shaping our digital future.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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