The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 23, 2021
Filed:
Oct. 14, 2019
Intel Corporation, Santa Clara, CA (US);
Ren Wang, Portland, OR (US);
Yipeng Wang, Hillsboro, OR (US);
Andrew Herdrich, Hillsboro, OR (US);
Jr-Shian Tsai, Portland, OR (US);
Tsung-Yuan C. Tai, Portland, OR (US);
Niall D. McDonnell, Limerick, IE;
Hugh Wilkinson, Newton, MA (US);
Bradley A. Burres, Waltham, MA (US);
Bruce Richardson, Claire, IE;
Namakkal N. Venkatesan, Hillsboro, OR (US);
Debra Bernstein, Sudbury, MA (US);
Edwin Verplanke, Chandler, AZ (US);
Stephen R. Van Doren, Portland, OR (US);
An Yan, Orefield, PA (US);
Andrew Cunningham, Ennis, IE;
David Sonnier, Austin, TX (US);
Gage Eads, Austin, TX (US);
James T. Clee, Orefield, PA (US);
Jamison D. Whitesell, Allentown, PA (US);
Jerry Pirog, Easton, PA (US);
Jonathan Kenny, Galway, IE;
Joseph R. Hasting, Orefield, PA (US);
Narender Vangati, Austin, TX (US);
Stephen Miller, Round Rock, TX (US);
Te K. Ma, Allentown, PA (US);
William Burroughs, Macungie, PA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache ('LLC'), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.