Intel Corporation

Sk Hynix Nand Product Solutions Corp.

Bradley A Burres

Gilbert M Wolrich

Wajdi K Feghali

Kamal J Koshy

Matthew James Adiletta

Ramamurthy Krithivas

Kirk S Yap

Jose Niell

Vinodh Gopal

Shay Gueron

Pankaj Kumar

Tsung-Yuan Charles Tai

Reshma Lal

Jaroslaw Sydir

Mark A Schmisseur

William Ralph Wheeler

Michael T Klinglesmith

Sivakumar Radhakrishnan

Eric Dahlen

Sin Sim Tan

Thomas M Slaight

Ren Wang

Andrew J Herdrich

Debra Bernstein

Jr-Shian Tsai

David Sonnier

Edwin Verplanke

William G Burroughs

Hugh Wilkinson

Namakkal N Venkatesan

Sujoy Sen

Aaron Gorius

Brian M Leitner

Geetani R Edirisooriya

Balaji Parthasarathy

Marc Tim Jones

David C Lee

Matthew R Wilcox

Pawel Szymanski

Kenneth C Haren

Yi-Feng Liu

Saptarshi Mondal

Stephen R Van Doren

Yadong Li

Niall D McDonnell

Amit Kumar

Yipeng Wang

Andrew Cunningham

Bruce Richardson

James T Clee

Chen-Chi Kuo

Narender R Vangati

Jerry Pirog

Joseph R Hasting

Te Khac Ma

Gage Eads

Jonathan Kenny

Stephen Miller

Donald C Soltis, Jr

An Yan

Kiel Boyle

Jamison D Whitesell

Thomas E Willis

William C Hasenplaugh

Scott David Peterson

Karl P Brummel

Duane E Galbi

Chengda Yang

Gunnar Gaubatz

Mrittika Ganguli

Tony Hurson

Salma Mirza

William Duggan

Salma Mirza Johnson

Keith Shaw

David Noeldner

Gilbert M Woolrich

Jeongnim Kim

Anandhi Jayakumar

Examples described herein relate to a network interface device that includes circuitry to perform operations, offloaded from a host, to identify at least one locator of at least one target storage associated with a storage access command based on operations selected from among multiple available operations, wherein the available operations comprise two or more: entry lookup by the network interface device, hash-based calculation on the network interface device, or control plane processing on the network interface device.

Initiator-side offload for scale-out storage

Methods and apparatus for Virtual Machine (VM) encryption of block storage with end-to-end data integrity protection in a SmartNIC. For a Write operation, the NIC is configured to encrypt a data block, append the encrypted data block with protection information (PI) generated using data in the data block to generate a protected data block and forward the protected data block onto a network or fabric to be delivered to a storage node. For a Read operation, the NIC is configured to receive a protected data block comprising cipher text including encrypted payload data concatenated with an encrypted inner PI and an outer PI, use the inner and outer PIs to perform PI checks, decrypt the cipher text to extract payload data, and forward or write at least the payload to a host. The inner and outer PIs and data formats are compliant with an NVMe specification.

VM encryption of block storage with end-to-end data integrity protection in a SmartNIC

Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.

Dynamic configuration of input/output controller access lanes

In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.

Presentation of direct accessed storage under a logical drive model

Examples described herein relate to migrating a virtualized execution environment from a first platform to a second platform while retaining use of namespace identifiers and permitting issuance of storage transactions by the virtualized execution environment. The first platform can include a first central processing unit or a first network interface. The second platform can include a central processing unit that is different that the first central processing unit and a network interface that is the same or different than the first network interface. The second platform can retain access permissions and target media format independent of one or more identifiers associated with the migrated virtualized execution environment at the second platform. Unperformed storage transactions can be migrated to the second platform for execution.

Maintaining storage namespace identifiers for live virtualized execution environment migration

Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache ('LLC'), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

Multi-core communication acceleration using hardware queue device

Technologies for flexible I/O protocol acceleration include a computing device having a root complex, a smart endpoint coupled to the root complex, and an offload complex coupled to the smart endpoint. The smart endpoint receives an I/O transaction that originates from the root complex and parses the I/O transaction based on an I/O protocol and identifies an I/O command. The smart endpoint may parse the I/O transaction based on endpoint firmware that may be programmed by the computing device. The smart endpoint accelerates the I/O command and provides a smart context to the offload complex. The smart endpoint may copy the I/O command to memory of the smart endpoint or the offload complex. The smart endpoint may identify protocol data based on the I/O command and copy the protocol data to the memory of the smart endpoint or the offload complex. Other embodiments are described and claimed.

Technologies for flexible protocol acceleration

An integrated circuit (IC) provisioned for asset protection has a primary circuit portion, such as a microprocessor or system-on-chip, that can be selectively disabled and enabled via an operability control input. The IC includes a secure register to store lock state indicia and unlock criteria, where a signal at the operability control input is responsive to the lock state indicia. In operation, a firmware data store receives and stores firmware code that includes a lock/unlock command, and firmware data that includes an unlock key. An authorization module verifies authenticity of the firmware code. A lock/unlock (LUL) module is operative to write lock state indicia to the secure register based on the lock/unlock command only in response to a positive verification of the authenticity of the firmware code by the authorization module, and to write lock state indicia to the secure register.

Asset protection of integrated circuits during transport

A SATA-compatible storage controller that can be configured to allow computers assigned to multiple different computer domains connected by at least one switch fabric to share resources of a common set of storage devices. The storage controller includes a plurality of virtual storage controllers, each providing an interface to a respective computer domain connected to the switch fabric, a virtualization mechanism configured to implement link layer virtualization for the common set of storage devices, and a split serial advanced technology attachment (SATA) protocol stack, the processing of which is partitioned between the respective virtual storage controllers and the virtualization mechanism.

Link layer virtualization in SATA controller

Growing community of inventors

Cambridge, MA, United States of America

Bradley A Burres