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San Jose, CA, United States of America

Arun K Gunda

USPTO Granted Patents = 11

Average Co-Inventor Count = 2.8

ph-index = 6

Forward Citations = 119(Granted Patents)

Location History:

Sunnyvale, CA (US) (1997 - 2001)
San Jose, CA (US) (2002 - 2014)

Company Filing History:

Lsi Corporation

Lsi Logic Corporation

Years Active: 1997-2014

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11 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 8627160 - System and device for reducing instantaneous voltage droop during a scan shift operation (2014-01-07),

2. 8418008 - Test technique to apply a variable scan clock including a scan clock modifier on an integrated circuit (2013-04-09),

3. 7831876 - Testing a circuit with compressed scan chain subsets (2010-11-09),

4. 7555688 - Method for implementing test generation for systematic scan reconfiguration in an integrated circuit (2009-06-30),

5. 7461315 - Method and system for improving quality of a circuit through non-functional test pattern identification (2008-12-02),

6. 7461307 - System and method for improving transition delay fault coverage in delay fault tests through use of an enhanced scan flip-flop (2008-12-02),

7. 7293210 - System and method for improving transition delay fault coverage in delay fault tests through use of transition launch flip-flop (2007-11-06),

8. 6449751 - Method of analyzing static current test vectors with reduced file sizes for semiconductor integrated circuits (2002-09-10),

9. 6212655 - IDDQ test solution for large asics (2001-04-03),

10. 5903578 - Test shells for protecting proprietary information in asic cores (1999-05-11),

11. 5663967 - Defect isolation using scan-path testing and electron beam probing in (1997-09-02),

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