The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 30, 2009
Filed:
Apr. 26, 2005
Method for implementing test generation for systematic scan reconfiguration in an integrated circuit
Applicants:
Ahmad A. Alvamani, Santa Clara, CA (US);
Narendra Devta-prasanna, Bangalore, IN;
Arun Gunda, San Jose, CA (US);
Inventors:
Ahmad A. Alvamani, Santa Clara, CA (US);
Narendra Devta-Prasanna, Bangalore, IN;
Arun Gunda, San Jose, CA (US);
Assignee:
LSI Logic Corporation, Milpitas, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract
A method for implementing test generation for systematic scan reconfiguration in an integrated circuit is presented. The method may comprise: defining at least one set of detectable faults; setting an SAS decoder configuration, the SAS decoder configuration including a don't-care bit; generating an ATPG pattern; and applying the ATPG pattern to one or more scan chain segments having a segment address associated with the SAS decoder configuration.