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Bengaluru, India

Narendra Devta-Prasanna

This inventor holds 7 USPTO granted patents. Top assignees: Lsi Corporation, Lsi Logic Corporation. Active years: 2007-2014.

USPTO Granted Patents = 7

% Patents Active = 14.3

Average Co-Inventor Count = 2.0

ph-index = 4

Forward Citations = 45(Granted Patents)

Location History:

Bengaluru, IN (2007 - 2010)
San Jose, CA (US) (2013 - 2014)

Company Filing History:

Lsi Corporation

Lsi Logic Corporation

Years Active: 2007-2014

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7 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 8627160 - System and device for reducing instantaneous voltage droop during a scan shift operation (2014-01-07),

2. 8412994 - Design-for-test technique to reduce test volume including a clock gate controller (2013-04-02),

3. 7802159 - Enhanced logic built-in self-test module and method of online system testing employing the same (2010-09-21),

4. 7555688 - Method for implementing test generation for systematic scan reconfiguration in an integrated circuit (2009-06-30),

5. 7461315 - Method and system for improving quality of a circuit through non-functional test pattern identification (2008-12-02),

6. 7461307 - System and method for improving transition delay fault coverage in delay fault tests through use of an enhanced scan flip-flop (2008-12-02),

7. 7293210 - System and method for improving transition delay fault coverage in delay fault tests through use of transition launch flip-flop (2007-11-06),

Profile summary based on public USPTO records.

Please report any incorrect information to [email protected]

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