The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 2008
Filed:
May. 06, 2005
Arun Gunda, San Jose, CA (US);
Narendra Devta-prasanna, Bangalore, IN;
Arun Gunda, San Jose, CA (US);
Narendra Devta-Prasanna, Bangalore, IN;
LSI Corporation, Milpitas, CA (US);
Abstract
The present invention is directed to a system and method for improving transition delay test coverage through use of enhanced flip flops (ES flip-flops) for a broadside test approach. Each ES flip-flop includes a two port flip-flop including a first flip-flop and a second flip-flop. A separate control input (ESM) which is not time critical is used to select a multiplexer of the second flip-flop. Thus, the ES flip-flops do not require a fast signal switching between launch and test response capture or an extra clock signal. Various enhanced scan modes may be selected via a combination of SEN and ESM. Moreover, only a heuristically selected subset of scan flip-flops may be replaced with the ES flip-flops so as to minimize the length of a scan chain as well as the logic area overhead. The present invention provides high TDF coverage under the broadside testing.