The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 11, 1999
Filed:
Mar. 08, 1996
Kaushik De, San Jose, CA (US);
Siva Venkatraman, Sunnyvale, CA (US);
Arun Gunda, Sunnyvale, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A reduced netlist representing only partial netlist information for a logic block such as an ASIC embedded core is generated, such that proprietary information contained within the netlist can be kept confidential. The core is conceptually divided into a first section that can be completely tested using only a serial scan port, and a second section that can be tested in isolation from the first section using both primary inputs to the core as well as scan inputs. Netlist information for the first section is removed from the netlist, and the customer is supplied with serial scan test vectors that test the first section. Additionally, a multiplexing circuit selects either a serial scan chain for the entire logic block, or a scan chain that does not include scan cells within the first section of the logic bloc.