For the Inventor, By the Inventor

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Cupertino, CA, United States of America

Ventana Micro Systems Inc.

USPTO Granted Patents = 70

Forward Citations = 49

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8 inventors (with patents filed for the assignee):

John G Favor (70 out of 70 patents)

Srivatsan Srinivasan (38 out of 38 patents)

Michael N Michael (24 out of 24 patents)

4. Robert Haskell Utley (9 out of 9 patents)

5. David S Oliver (6 out of 7 patents)

6. Vihar Soneji (3 out of 3 patents)

7. Kelvin D Goveas (1 out of 1 patent)

8. David A Kruckemyer (1 out of 1 patent)

Core Competencies:

Microprocessor

Cache Coherency

Power Management

Side Channel Attacks

Physical Address Proxies

Multi-Fetch Block

Loop Iteration

Branch Target Buffer

Translation Context

Load/Store Instructions

Predictor Unit

Instruction Fetch Pipeline

70 patents: Sort by Forward Citations

1. 12693864 - Microprocessor that performs mid-fetch block restart abort processing (2026-07-28),

2. 12566702 - Physical address proxy reuse management (2026-03-03),

3. 12560993 - Power management of devices with differentiated power scaling based on relative power benefit estimation (2026-02-24),

4. 12524538 - Processor that mitigates side channel attacks by preventing cache memory state from being affected by a missing load operation by inhibiting or canceling a fill request of the load operation if an older load generates a need for an architectural exception (2026-01-13),

5. 12499050 - Physical address proxy (PAP) residency determination for reduction of PAP reuse (2025-12-16),

6. 12498933 - Prediction unit that predicts successor fetch block start address of multi-fetch block macro-op cache entry (2025-12-16),

7. 12498929 - Microprocessor that performs partial fallback abort processing of multi-fetch block macro-op cache entries (2025-12-16),

8. 12498928 - Microprocessor that builds multi-fetch block macro-op cache entries in two-stage process (2025-12-16),

9. 12498927 - Microprocessor that allows same-fetch block start address co-residence of unrolled loop multi-fetch block macro-op cache entry and loop body macro-op cache entry used to build same (2025-12-16),

10. 12498926 - Microprocessor that builds consistent loop iteration count unrolled loop multi-fetch block macro-op cache entries (2025-12-16),

11. 12493558 - Using physical address proxies to accomplish penalty-less processing of load/store instructions whose data straddles cache line address boundaries (2025-12-09),

12. 12493469 - Microprocessor that extends sequential multi-fetch block macro-op cache entries (2025-12-09),

13. 12493468 - Microprocessor that performs mid-macro-op cache entry restart abort processing (2025-12-09),

14. 12493466 - Microprocessor that builds inconsistent loop that iteration count unrolled loop multi-fetch block macro-op cache entries (2025-12-09),

15. 12487939 - Virtually-indexed cache coherency using physical address proxies (2025-12-02),

Ventana Micro Systems Inc. is a leading provider of innovative hardware solutions for the microelectronics industry. The company specializes in designing and manufacturing precision tools for semiconductor wafer processing, including ion implantation and wafer metrology. With a focus on quality, reliability, and performance, Ventana Micro Systems Inc. is committed to helping customers achieve higher productivity and efficiency in their manufacturing processes.

This text is generated by artificial intelligence and may not be accurate.

Company Badge

USPTO Data Jan 1 1976 - Sep 15 2026

70 Patents

#9 in Cupertino, CA

#1,220 in California

#5,224 in US

#10,607 in the World

Cupertino, CA, United States of America

Ventana Micro Systems Inc.

Forward Citations = 49

8 inventors:

John G Favor (70 out of 70 patents)

Srivatsan Srinivasan (38 out of 38 patents)

Michael N Michael (24 out of 24 patents)

4. Robert Haskell Utley (9 out of 9 patents)

5. David S Oliver (6 out of 7 patents)

Please report any incorrect information to [email protected]

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