Microprocessor that builds inconsistent loop that iteration count unrolled loop multi-fetch block macro-op cache entries

Abstract

A microprocessor includes a prediction unit (PRU) that predicts a sequence of fetch blocks (FBlks) in a program instruction stream, a macro-op (MOP) cache (MOC) that comprises MOC entries (MEs), a fusion engine. An ME holds MOPs into which architectural instructions of one or more FBlks are decoded. The PRU detects a loop body ME within the program instruction stream, accumulates loop iteration count information about a series of instances of a loop on the loop body ME in the program instruction stream, updates a consistency counter of the loop body ME while accumulating the loop iteration count information, and in response to detecting that the consistency counter has reached a threshold, instructs the fusion engine to use F copies of the MOPs of the loop body ME to build in the MOC an unrolled loop multi-FBlk ME; F is a loop unroll factor that is at least two.