For the Inventor, By the Inventor

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San Jose, CA, United States of America

Silicon Valley Group, Inc.

Calculating rank

USPTO Granted Patents = 47

% Expired Patents = 4.3

Trademarks = 6

Forward Citations = 1,687

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93 inventors (with patents filed for the assignee):

Emir Gurer (8 out of 20 patents)

Johann Tam (5 out of 5 patents)

Ed C Lee (4 out of 14 patents)

4. Reese Reynolds (3 out of 16 patents)

5. Don Roy Sauer (3 out of 45 patents)

6. Alexander H Slocum (3 out of 34 patents)

7. Edmond R Ward (3 out of 49 patents)

8. Tom Zhong (3 out of 10 patents)

9. James C Grambow (3 out of 6 patents)

10. Donald R Sauer (3 out of 9 patents)

11. Christopher T Ratliff (3 out of 7 patents)

12. Robert Parkash Mandal (3 out of 41 patents)

13. John W Lewellen (3 out of 10 patents)

14. Matthew J Van Doren (3 out of 4 patents)

15. Jeffrey M Kowalski (3 out of 3 patents)

Core Competencies:

Wafer Processing

Lithography Tool

Optical Reduction

Thermal Management

Photoresist Coating

Plasma Deposition

Chemical Delivery

Substrate Coating

Yield Performance

Scanning Apparatus

Adaptive Process Control

Dual Isolation System

47 patents: Sort by Forward Citations

1. 6616394 - Apparatus for processing wafers (2003-09-09),

2. 6570713 - Method and apparatus for optimizing the output beam characteristics of a laser (2003-05-27),

3. 6538720 - Lithographic tool with dual isolation system and method for configuring the same (2003-03-25),

4. 6522483 - Optical reduction system with elimination of reticle diffraction induced bias (2003-02-18),

5. 6509952 - Method and system for selective linewidth optimization during a lithographic process (2003-01-21),

6. 6480330 - Ultraviolet polarization beam splitter for microlithography (2002-11-12),

7. 6472643 - Substrate thermal management system (2002-10-29),

8. 6468586 - Environment exchange control for material on a wafer surface (2002-10-22),

9. 6418356 - Method and apparatus for resolving conflicts in a substrate processing system (2002-07-09),

10. 6416318 - Process chamber assembly with reflective hot plate and pivoting lid (2002-07-09),

11. 6414276 - Method for substrate thermal management (2002-07-02),

12. 6387602 - Apparatus and method of cleaning reticles for use in a lithography tool (2002-05-14),

13. 6369874 - Photoresist outgassing mitigation system method and apparatus for in-vacuum lithography (2002-04-09),

14. 6327793 - Method for two dimensional adaptive process control of critical dimensions during spin coating process (2001-12-11),

15. 6324003 - Calcium fluoride (CaF2) stress plate and method of making the same (2001-11-27),

Company Overview

Silicon Valley Group, Inc., based in San Jose, California, specializes in advanced technologies for semiconductor manufacturing. The company focuses on wafer processing and lithography, providing innovative solutions in optical systems, thermal management, and photoresist coating. Additionally, it develops chemical delivery systems and plasma deposition techniques, enhancing substrate coating processes. With a commitment to advancing semiconductor technology, Silicon Valley Group plays a crucial role in the evolution of the microelectronics industry.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 20 2026

47 Patents

#194 in San Jose, CA

#1,752 in California

#7,440 in US

#14,827 in the World

San Jose, CA, United States of America

Silicon Valley Group, Inc.

Forward Citations = 1,687

93 inventors:

Emir Gurer (8 out of 20 patents)

Johann Tam (5 out of 5 patents)

Ed C Lee (4 out of 14 patents)

4. Reese Reynolds (3 out of 16 patents)

5. Don Roy Sauer (3 out of 45 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Silicon Valley Group, Inc.. Retrieved from https://idiyas.com/company/silicon-valley-group

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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