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San Jose, CA, United States of America

Nptest, Inc.

USPTO Granted Patents = 17

Forward Citations = 184

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32 inventors (with patents filed for the assignee):

Burnell G West (3 out of 37 patents)

Gary A Wells (3 out of 4 patents)

Chun-Cheng Tsao (2 out of 12 patents)

4. Kenneth R Wilsher (2 out of 18 patents)

5. Daniel A Rosenthal (1 out of 7 patents)

6. Kenichi Kanai (1 out of 16 patents)

7. William A Fritzsche (1 out of 14 patents)

8. Francis Ho (1 out of 7 patents)

9. Frank Sauk (1 out of 3 patents)

10. Howard Maassen (1 out of 6 patents)

11. Chris A Shmatovich (1 out of 3 patents)

12. Theodore R Lundquist (1 out of 24 patents)

13. Erwan Le Roy (1 out of 9 patents)

14. Jamie S Cullen (1 out of 5 patents)

15. Toshihiro Nomura (1 out of 2 patents)

17 patents: Sort by Forward Citations

1. 6940271 - Pin electronics interface circuit (2005-09-06),

2. 6872581 - Measuring back-side voltage of an integrated circuit (2005-03-29),

3. 6855622 - Method and apparatus for forming a cavity in a semiconductor substrate using a charged particle beam (2005-02-15),

4. 6853941 - Open-loop for waveform acquisition (2005-02-08),

5. 6822435 - Comparator circuit for differential swing comparison and common-mode voltage comparison (2004-11-23),

6. 6794861 - Method and apparatus for socket calibration of integrated circuit testers (2004-09-21),

7. 6781218 - Method and apparatus for accessing internal nodes of an integrated circuit using IC package substrate (2004-08-24),

8. 6775637 - Test method and apparatus for source synchronous signals (2004-08-10),

9. 6760223 - Apparatus and method for contacting device with delicate light-transparent pane (2004-07-06),

10. 6748564 - Scan stream sequencing for testing integrated circuits (2004-06-08),

11. 6744267 - Test system and methodology (2004-06-01),

12. 6737853 - Photoconductive-sampling voltage measurement (2004-05-18),

13. 6672947 - Method for global die thinning and polishing of flip-chip packaged integrated circuits (2004-01-06),

14. 6661836 - Measuring jitter of high-speed data channels (2003-12-09),

15. 6630667 - Compact, high collection efficiency scintillator for secondary electron detection (2003-10-07),

NPTest, Inc. is a leading provider of advanced semiconductor test solutions and services. With a wide range of cutting-edge technologies, NPTest helps semiconductor manufacturers optimize their testing processes, improve yields, and reduce time-to-market. Their comprehensive suite of test solutions includes wafer probe, final test, and system level test, enabling customers to achieve higher test efficiencies and cost-effective production. Backed by a team of industry experts and innovative solutions, NPTest continues to be a trusted partner for semiconductor companies worldwide.

This text is generated by artificial intelligence and may not be accurate.

Company Badge

USPTO Data Jan 1 1976 - Dec 9 2025

17 Patents

#355 in San Jose, CA

#4,369 in California

#18,300 in US

#34,819 in the World

San Jose, CA, United States of America

Nptest, Inc.

Forward Citations = 184

32 inventors:

Burnell G West (3 out of 37 patents)

Gary A Wells (3 out of 4 patents)

Chun-Cheng Tsao (2 out of 12 patents)

4. Kenneth R Wilsher (2 out of 18 patents)

5. Daniel A Rosenthal (1 out of 7 patents)

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