For the Inventor, By the Inventor

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San Jose, CA, United States of America

Nptest, Inc.

Calculating rank

USPTO Granted Patents = 17

% Expired Patents = 23.5

Forward Citations = 185

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32 inventors (with patents filed for the assignee):

Burnell G West (3 out of 37 patents)

Gary A Wells (3 out of 4 patents)

Chun-Cheng Tsao (2 out of 12 patents)

4. Kenneth R Wilsher (2 out of 18 patents)

5. Daniel A Rosenthal (1 out of 7 patents)

6. Kenichi Kanai (1 out of 18 patents)

7. William A Fritzsche (1 out of 14 patents)

8. Francis Ho (1 out of 7 patents)

9. Frank Sauk (1 out of 3 patents)

10. Howard Maassen (1 out of 6 patents)

11. Chris A Shmatovich (1 out of 3 patents)

12. Theodore R Lundquist (1 out of 24 patents)

13. Erwan Le Roy (1 out of 9 patents)

14. Jamie S Cullen (1 out of 5 patents)

15. Toshihiro Nomura (1 out of 2 patents)

17 patents: Sort by Forward Citations

1. 6940271 - Pin electronics interface circuit (2005-09-06),

2. 6872581 - Measuring back-side voltage of an integrated circuit (2005-03-29),

3. 6855622 - Method and apparatus for forming a cavity in a semiconductor substrate using a charged particle beam (2005-02-15),

4. 6853941 - Open-loop for waveform acquisition (2005-02-08),

5. 6822435 - Comparator circuit for differential swing comparison and common-mode voltage comparison (2004-11-23),

6. 6794861 - Method and apparatus for socket calibration of integrated circuit testers (2004-09-21),

7. 6781218 - Method and apparatus for accessing internal nodes of an integrated circuit using IC package substrate (2004-08-24),

8. 6775637 - Test method and apparatus for source synchronous signals (2004-08-10),

9. 6760223 - Apparatus and method for contacting device with delicate light-transparent pane (2004-07-06),

10. 6748564 - Scan stream sequencing for testing integrated circuits (2004-06-08),

11. 6744267 - Test system and methodology (2004-06-01),

12. 6737853 - Photoconductive-sampling voltage measurement (2004-05-18),

13. 6672947 - Method for global die thinning and polishing of flip-chip packaged integrated circuits (2004-01-06),

14. 6661836 - Measuring jitter of high-speed data channels (2003-12-09),

15. 6630667 - Compact, high collection efficiency scintillator for secondary electron detection (2003-10-07),

Company Overview

Nptest, Inc. is a technology company based in San Jose, California, specializing in advanced testing solutions for semiconductor and electronic devices. The organization focuses on developing innovative methodologies and tools that enhance the reliability and performance of electronic systems. With a commitment to quality and precision, Nptest serves a diverse range of industries, contributing to the advancement of technology through rigorous testing and validation processes.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Nov 3 2026

17 Patents

#383 in San Jose, CA

#4,521 in California

#18,914 in US

#35,988 in the World

San Jose, CA, United States of America

Nptest, Inc.

Forward Citations = 185

32 inventors:

Burnell G West (3 out of 37 patents)

Gary A Wells (3 out of 4 patents)

Chun-Cheng Tsao (2 out of 12 patents)

4. Kenneth R Wilsher (2 out of 18 patents)

5. Daniel A Rosenthal (1 out of 7 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Nptest, Inc.. Retrieved from https://idiyas.com/company/nptest

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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