The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 01, 2004

Filed:

Jul. 16, 2002
Applicant:
Inventors:

Frank M. Sauk, San Ramon, CA (US);

Gary A. Wells, Fremont, CA (US);

Thomas P. Ho, Los Altos, CA (US);

Assignee:

NPTest, LLC, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 3/102 ;
U.S. Cl.
CPC ...
G01R 3/102 ;
Abstract

A test system for testing an electronic device is deployable in two basic configurations. In one of the configurations, a load board ( ) that receives a unit ( ) of the device is directly attached to a test head ( ). In the other configuration, the same load board or one having largely the same pattern of test-head signal transmission positions is coupled through an interface apparatus ( ) to a test head. A probe system ( ) contacts that load board or/and the interface apparatus. The interface apparatus is normally configured to largely prevent test-head vibrations from being transferred to the probe system. Additionally or alternatively, the load board is vacuum attached to the interface apparatus.


Find Patent Forward Citations

Sauk, Frank. (2004). Test system and methodology (U.S. Patent No. 6744267). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6744267

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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