The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 2018

Filed:

Jun. 28, 2016
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Shing-Chao Chen, Zhubei, TW;

Chih-Wei Lin, Zhubei, TW;

Meng-Tse Chen, Changzhi Township, Pingtung County, TW;

Hui-Min Huang, Taoyuan, TW;

Ming-Da Cheng, Zhubei, TW;

Kuo-Lung Pan, Hsinchu, TW;

Wei-Sen Chang, Jinsha Township, Kinmen County, TW;

Tin-Hao Kuo, Hsinchu, TW;

Hao-Yi Tsai, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 21/48 (2006.01); H01L 23/31 (2006.01); H01L 23/58 (2006.01);
U.S. Cl.
CPC ...
H01L 21/566 (2013.01); H01L 21/486 (2013.01); H01L 21/568 (2013.01); H01L 23/315 (2013.01); H01L 23/3114 (2013.01); H01L 23/585 (2013.01);
Abstract

Structures and formation methods of a chip package are provided. The method includes forming multiple conductive structures over a carrier substrate and disposing a semiconductor die over the carrier substrate. The method also includes disposing a mold over the carrier substrate. The method further includes forming a protection layer between the mold and the carrier substrate to surround the semiconductor die and the conductive structures. In addition, the method includes removing the mold.


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