The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 27, 2018

Filed:

Dec. 24, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Willy Rachmady, Beaverton, OR (US);

Matthew V. Metz, Portland, OR (US);

Chandra S. Mohapatra, Beaverton, OR (US);

Gilbert Dewey, Hillsboro, OR (US);

Nadia M. Rahhal-Orabi, Hillsboro, OR (US);

Tahir Ghani, Portland, OR (US);

Anand S. Murthy, Portland, OR (US);

Jack T. Kavalieros, Portland, OR (US);

Glenn A. Glass, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 29/06 (2006.01); H01L 21/306 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7853 (2013.01); H01L 21/02532 (2013.01); H01L 21/02694 (2013.01); H01L 21/30625 (2013.01); H01L 21/76224 (2013.01); H01L 29/0653 (2013.01); H01L 29/66795 (2013.01);
Abstract

An embodiment includes a microelectronic device comprising: a substrate comprising a raised portion and a non-raised portion, wherein a dielectric material is disposed adjacent the raised portion, an epitaxial sub-fin structure disposed on the raised portion, wherein a bottom portion of the epitaxial sub-fin structure comprises an asymmetric profile, and an epitaxial fin device structure disposed on the sub-fin structure. Other embodiments are described herein.


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