The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 25, 2017

Filed:

Oct. 20, 2015
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Bor-Zen Tien, Hsin-Chu, TW;

Jhu-Ming Song, Nantou, TW;

Hsuan-Han Lin, Kaohsiung, TW;

Kuang-Hsin Chen, Jung-Li, TW;

Mu-Yi Lin, Taichung, TW;

Tzong-Sheng Chang, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 23/00 (2006.01); H01L 21/285 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76849 (2013.01); H01L 21/02271 (2013.01); H01L 21/28008 (2013.01); H01L 21/2855 (2013.01); H01L 21/28556 (2013.01); H01L 21/31116 (2013.01); H01L 21/76807 (2013.01); H01L 21/76843 (2013.01); H01L 21/76877 (2013.01); H01L 23/53238 (2013.01); H01L 24/00 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 21/28562 (2013.01); H01L 23/53228 (2013.01); H01L 2221/1015 (2013.01); H01L 2224/0345 (2013.01); H01L 2224/0361 (2013.01); H01L 2224/03452 (2013.01); H01L 2224/05027 (2013.01); H01L 2224/05082 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05181 (2013.01); H01L 2224/05186 (2013.01); H01L 2224/05559 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/05573 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05639 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05684 (2013.01); H01L 2924/04953 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/13091 (2013.01);
Abstract

A method comprises forming a plurality of interconnect components over a gate structure, wherein a bottom metal line of the interconnect components is connected to the gate structure through a gate plug, depositing a dielectric layer over a top metal line of the interconnect components, forming an opening in the dielectric layer, depositing a first barrier layer on a bottom and sidewalls of the opening using a non-plasma based deposition process, depositing a second barrier layer over the first barrier layer using a plasma based deposition process and forming a pad in the opening.


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