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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9684236 B1

PDFFull Text
Expired
Date of Patent:
Jun. 20, 2017

Filed:

Mar. 17, 2016

Method of patterning a film layer

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Ken-Hsien Hsieh, Taipei, TW;

Kuan-Hsin Lo, Nantou County, TW;

Shih-Ming Chang, Hsinchu County, TW;

Wei-Liang Lin, Hsin-Chu, TW;

Joy Cheng, Hsin-Chu, TW;

Chun-Kuang Chen, Hsinchu County, TW;

Ching-Yu Chang, Yilang County, TW;

Kuei-Shun Chen, Hsinchu, TW;

Ru-Gun Liu, Hsinchu County, TW;

Tsai-Sheng Gau, HsinChu, TW;

Chin-Hsiang Lin, Hsin-Chu, TW;

Assignee:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Attorney:

Haynes and Boone, LLP

Primary Examiner:

Amanda C Walke

Int. Cl.
CPC ...
G03F 7/11 (2006.01); G03F 7/40 (2006.01); G03F 7/00 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 21/02 (2006.01); H01L 21/3213 (2006.01); G03F 7/20 (2006.01); G03F 7/16 (2006.01); G03F 7/32 (2006.01); H01L 21/027 (2006.01); B82Y 10/00 (2011.01); B82Y 40/00 (2011.01); H01L 21/3065 (2006.01);
U.S. Cl.
CPC ...
G03F 7/002 (2013.01); B82Y 10/00 (2013.01); B82Y 40/00 (2013.01); G03F 7/165 (2013.01); G03F 7/20 (2013.01); G03F 7/2022 (2013.01); G03F 7/2059 (2013.01); G03F 7/32 (2013.01); G03F 7/40 (2013.01); H01L 21/0274 (2013.01); H01L 21/02112 (2013.01); H01L 21/02118 (2013.01); H01L 21/02318 (2013.01); H01L 21/3065 (2013.01); H01L 21/3081 (2013.01); H01L 21/3086 (2013.01); H01L 21/31138 (2013.01); H01L 21/31144 (2013.01); H01L 21/32139 (2013.01);
Abstract

A method of fabricating a semiconductor device is disclosed. The method includes forming a first patterned hard mask over a material layer. The first patterned hard mask defines an opening. The method also includes forming a direct-self-assembly (DSA) layer having a first portion and a second portion within the opening, removing the first portion of the DSA layer, forming spacers along sidewalls of the second portion of the DSA layer and removing the second portion of the DSA layer. The spacers form a second patterned hard mask over the material layer.

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