The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 2017

Filed:

Jan. 29, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Ryan Chia-Jen Chen, Taiwan, TW;

Jr-Jung Lin, Hsinchu, TW;

Chien-Hao Chen, Chuangwei Township, TW;

Yi-Hsing Chen, Changhua, TW;

Kuo-Tai Huang, HsinChu, TW;

Yih-Ann Lin, Jhudong Township, TW;

Yi-Shien Mor, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 21/82385 (2013.01); H01L 21/28088 (2013.01); H01L 21/823842 (2013.01); H01L 21/823857 (2013.01); H01L 27/0922 (2013.01); H01L 29/0653 (2013.01); H01L 29/401 (2013.01); H01L 29/42372 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01);
Abstract

A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region, forming a first dielectric layer over the semiconductor substrate, forming a first metal layer over the first dielectric layer, the first metal layer having a first work function, removing at least a portion of the first metal layer in the second region, and thereafter, forming a semiconductor layer over the first metal layer in the first region and over the at least partially removed first metal layer in the second region. The method further includes removing the semiconductor layer and forming a second metal layer on the first metal layer in the first region and on the at least partially removed first metal layer in the second region, the second metal layer having a second work function that is different than the first work function.


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