The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 14, 2017
Filed:
Sep. 10, 2015
Unity Semiconductor Corporation, Sunnyvale, CA (US);
Christophe J. Chevallier, Palo Alto, CA (US);
Steve Kuo-Ren Hsia, San Jose, CA (US);
Wayne Kinney, Emmett, ID (US);
Steven Longcor, Mountain View, CA (US);
Darrell Rinerson, Cupertino, CA (US);
John Sanchez, Palo Alto, CA (US);
Philip F. S. Swab, Santa Rosa, CA (US);
Edmond R. Ward, Monte Sereno, CA (US);
UNITY SEMICONDUCTOR CORPORATION, Sunnyvale, CA (US);
Abstract
A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO-LSCoO or LaNiO-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.