The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 19, 2016
Filed:
Dec. 11, 2013
Intel Corporation, Santa Clara, CA (US);
Omkar G. Karhade, Chandler, AZ (US);
John S. Guzek, Chandler, AZ (US);
Johanna M. Swan, Scottsdale, AZ (US);
Christopher J. Nelson, Gilbert, AZ (US);
Nitin A. Deshpande, Chandler, AZ (US);
William J. Lambert, Chandler, AZ (US);
Charles A. Gealer, Phoenix, AZ (US);
Feras Eid, Chandler, AZ (US);
Islam A. Salama, Chandler, AZ (US);
Kemal Aygun, Chandler, AZ (US);
Sasha N. Oster, Chandler, AZ (US);
Tyler N. Osborn, Gilbert, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction. An interconnect comprising an interconnect substrate having a plurality of electrically isolated conductive traces extending in the x-direction on a first surface of the interconnect substrate may be attached to the at least one first microelectronic device connection structure row and the at least one second microelectronic device connection structure row, such that at least one interconnect conductive trace forms a connection between a first microelectronic device connection structure and its corresponding second microelectronic device connection structure.