The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 16, 2016
Filed:
Nov. 01, 2013
Intel Corporation, Santa Clara, CA (US);
Ravi Pillarisetty, Portland, OR (US);
Jack T. Kavalieros, Portland, OR (US);
Willy Rachmady, Beaverton, OR (US);
Uday Shah, Portland, OR (US);
Benjamin Chu-Kung, Hillsboro, OR (US);
Marko Radosavljevic, Beaverton, OR (US);
Niloy Mukherjee, Beaverton, OR (US);
Gilbert Dewey, Hillsboro, OR (US);
Been-Yih Jin, Lake Oswego, OR (US);
Robert S. Chau, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.