The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 16, 2016
Filed:
Jun. 02, 2014
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Hung-Chun Wang, Taichung, TW;
Ching-Hsu Chang, Taipei County, TW;
Feng-Ju Chang, Hsinchu, TW;
Chun-Hung Wu, Hsinchu, TW;
Ping-Chieh Wu, Hsinchu County, TW;
Wen-Hao Liu, Hsinchu County, TW;
Ming-Hsuan Wu, Hsinchu County, TW;
Feng-Lung Lin, Hsinchu County, TW;
Cheng Kun Tsai, Hsinchu, TW;
Wen-Chun Huang, Tainan, TW;
Ru-Gun Liu, Hsinchu County, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
Provided is an integrated circuit (IC) manufacturing method. The method includes receiving a design layout of an IC, wherein the design layout includes a plurality of non-overlapping IC regions and each of the IC regions includes a same initial IC pattern. The method further includes dividing the IC regions into a plurality of groups based on a location effect analysis such that all IC regions in a respective one of the groups are to have substantially same location effect. The method further includes performing a correction to one IC region in each of the groups using a correction model that includes location effect; and copying the corrected IC region to other IC regions in the respective group. The method further includes storing the corrected IC design layout in a tangible computer-readable medium for use by a further IC process stage.