The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 26, 2016
Filed:
Sep. 26, 2013
Stats Chippac, Ltd., Singapore, SG;
KyungMoon Kim, Gyeonggi-do, KR;
KooHong Lee, Seoul, KR;
JaeHak Yee, Seoul, KR;
YoungChul Kim, Kyoungki-di, KR;
Lan Hoang, San Jose, CA (US);
Pandi C. Marimuthu, Singapore, SG;
Steve Anderson, San Ramon, CA (US);
HeeJo Chi, Kyoungki-do, KR;
STATS ChipPAC, Ltd., Singapore, SG;
Abstract
A semiconductor device has a semiconductor die disposed over a substrate. The semiconductor die and substrate are placed in a chase mold. An encapsulant is deposited over and between the semiconductor die and substrate simultaneous with bonding the semiconductor die to the substrate in the chase mold. The semiconductor die is bonded to the substrate using thermocompression by application of force and elevated temperature. An electrical interconnect structure, such as a bump, pillar bump, or stud bump, is formed over the semiconductor die. A flux material is deposited over the interconnect structure. A solder paste or SOP is deposited over a conductive layer of the substrate. The flux material and SOP provide temporary bond between the semiconductor die and substrate. The interconnect structure is bonded to the SOP. Alternatively, the interconnect structure can be bonded directly to the conductive layer of the substrate, with or without the flux material.